support for fpga bram generation
non-inlined memories will now export write mask granularity
Add updated AdvTester
Fix imports in AdvTester so it will compile under more common build environments
new versions of docs
merge
fix manual doc'ing mem
more robust write mask granularity detection
Support LDFLAGS
fgpa backend is basically same as verilog now
differences to be handled in mem generation by post-chisel scripts
Merge pull request #240 from colinschmidt/master

Support LDFLAGS
remove snapshot code
Updated commented tag.

We should really do this prior to publishing the release, even though
the git version (2.3-SNAPSHOT) will differ from the actual release
version (2.2.16).
getting started for cs250 and fixed manual
merge
Update documentation.

Remove old documents.
Update version.
Update copyright date.
Resurrect html versions of manual and getting-started.
Update reference to "current" release jar file.
Remove getting-started.html until we sort out the font/images problems.
Move bootcamp to the bottom of the docs list.
Delete "These are the most recent Chisel slides and contain many detailed pictures."
Merge branch 'master' of github.com:ucb-bar/chisel into dse

Conflicts:
	doc/getting-started/basics-guts.tex
	doc/getting-started/modules-guts.tex
	doc/getting-started/projects-guts.tex
	doc/getting-started/testing-guts.tex
	project/build.scala