PULSE_OUT singal in ch_sub_system is a clk for the t flipflop. this is
changed to flipflop enabled by the PULSE_OUT and whose clock signal is
SYS_CLK. This reduced the warning genereted during bitfile generation.
reverting back will not make any difference in the operation. Need to
more on the usage of CE pin for clock routed through combinational logic
In envelope_gen code is added in such a way the envelope will be shifted
bu 200x20ns.