Updated 003-00004 (PCB) and 001-00004 (Variant

Updated 003-00004 (PCB) and 001-00004 (variant, including schematic and
assembly) revisions. Both were A and both are now B
Moved the DDR3 decoupling caps away by 0.33mm

The decoupling caps interfered with the placement of the DDR3 IC (U11).
While moving the parts the teardrops were removed. They will be
regenerated before rev B is released.
Changed U1 footprint pad size

Changed the ECP5 CSG324 footprint from 0.25mm to 0.34mm diameter pads.
When soldered to the 0.25mm pads the ECP5 FPGA adhered poorly to the
PCB. The 0.34mm pad size was chosen based on Altera AN114 application
note (Table 3).
Moved oscillator clock connection

Moved the oscillator clock connection on the ECP5 from A19 to B12. A19
was not a valid clock input.
Updated USB connector

The original Samtec part is now obsolete.
Various clean-up edits

1. Removed silly DNC on ECP5 schematic page
2. Changed 2x10 header to “Not Fitted”
3. Fixed DDR3 trace clearance error
Resolved all DRCs

Added a looser clearance rule for the 4 tightest expansion nets where
they escape the ECP5.
More cleanup

1. Adjusted U12’s resistor placement (they were too close to have any
solder mask between the different part’s pads)
2. Moved C81 and C82 away from the crystal a bit
Disconnected the FT2232HQ center pad.

Removed the connection from the FT2232HQ center pad and ground. The
datasheet does not specify what net the pad should be connected to. We
found use cases of the FT2232HQ on On Semi reference cards (ie.
EVBUM2216/D) that kept the pad isolated so we followed suit.
Updated teardrops
Updated OutJobs

The inner layers were not being generated with the gerbers.
Merge pull request #1 from jsloan256/Rev-B

Reviewed and accepting changes associated with Rev B