Revert "bcmdhd: update to 1.61.58 from google edition jf (4.3)"

This reverts commit 41e14ad8beb09eee3e23f16a4f5ad0b19233aeb9.
arm: LoUIS cache maintenance API
ARM: smp: Wait just 1 second for other CPU to halt
Currently, the busyloop waiting for a 2nd CPU to stop takes about 4
seconds.  Adjust for the overhead of the loop by looping every 1ms
instead of 1us.

Signed-off-by: Chris Fries <C.Fries@motorola.com>
Reviewed-on: http://gerrit.pcs.mot.com/537864
SLT-Approved: Slta Waiver <sltawvr@motorola.com>
Tested-by: Jira Key <jirakey@motorola.com>
Reviewed-by: Check Patch <CHEKPACH@motorola.com>
Reviewed-by: Klocwork kwcheck <klocwork-kwcheck@sourceforge.mot.com>
Reviewed-by: Igor Kovalenko <cik009@motorola.com>
Reviewed-by: Russell Knize <rknize2@motorola.com>
Submit-Approved: Jira Key <jirakey@motorola.com>
block: BFQ I/O scheduler v7r2 for linux 3.0.y
source: http://algo.ing.unimo.it/people/paolo/disk_sched/sources.php
net: Fix compile warnings
arm: mm: Fix compile warnings for dma
exynos: Fixes and mess cleanup
drivers: media: Fix compile warnings and cleanup

Conflicts:
	drivers/gpu/mali400/r3p2/mali/common/mali_kernel_mem_os.c
	drivers/gpu/mali400/r3p2/ump/linux/ump_osk_low_level_mem.c
	drivers/media/video/samsung/mali/platform/orion-m400/mali_platform_dvfs.c
drivers: video: Fix compile warnings and cleanup

Conflicts:
	drivers/video/samsung/mdnie.c
	drivers/video/samsung/s5p-dsim.c
drivers: power: Fix compile warnings and cleanup
drivers: input: Fix compile warnings and cleanup

Conflicts:
	drivers/input/keyboard/cypress/issp_main.c
drivers: mmc: Fix compile warnings and cleanup

Conflicts:
	drivers/mmc/core/quirks.c
drivers: misc: Fix compile warnings and cleanup
drivers: usb: Fix compile warnings and cleanup
drivers: Fix general compile warnings and cleanup

Conflicts:
	drivers/staging/zram/zram_drv.c
ARM: cache: assume 64-byte L1 cachelines for ARMv7 CPUs

To ensure correct alignment of cacheline-aligned data, the maximum
cacheline size needs to be known at compile time.

Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely
that there will be future ARMv7 implementations with the same line size)
then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline
size. For CPUs with smaller caches, this will result in some harmless
padding but will help with single zImage work and avoid hitting subtle
bugs with misaligned data structures.

Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
exynos: tmu: Fix warning and silence spam