Avoid a CPU memory fence, and better order memory barriers to accesses

Code produced by GCC 4.9's C11 atomic implementation does not seem to add a
CPU memory fence even with memory_order_seq_cst. Unnecessary memory fences
will be a detriment to performance, so they should only be added if needed.
Rename ATOMIC_COMPARE_EXCHANGE to ATOMIC_COMPARE_EXCHANGE_STRONG
Remove an unused function
Make the source's buffer queue head and current queue item atomic
Use atomics for the device and context list heads
Add some casts for inline assembly atomics

And remove an unnecessary void cast
Use the right type for atomic compare-exchange
Use an ATOMIC_INIT macro instead of ATOMIC_LOAD_UNSAFE
Fix some lock ordering to avoid potential deadlocks
Load fluidsynth dynamically when possible
Update alsoft-config

Adds Compressor effect and SSE 4.1 for exclusion, and alters the HRTF tables
tooltip to refer the the default data sets instead of the built-in set.
Filter for relative HRTF data paths and add Add/Remove label texts
Enable large file support