grouper-panel: tweak backlight values
fixup get rid of cputime64_add/sub

See 648616343cdbe904c585a6c12e323d3b3c72e46f

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Revert "ARM: tegra: clock: Don't fail clk_enable when max_rate has been lowered"

This reverts commit 8d351aa5478de533114e614f2607bc85ed23df91.

The above commit introduced recursive call of clk enable/set rate APIs
that may hang the system.

Change-Id: I04eff9e1c3ddee82f6d2e17690122cc41fad203f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/100710
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Update Tegra3 sclk and cbus dvfs tables

Updated 0.95V entries in Tegra3 dvfs tables for sclk and cbus clocks
with recent characterization results.

Bug 817679
Bug 841336

Change-Id: I892690aea4c584b34be5dbfcbcd8b35abd86a997
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107777
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: revjunkie <rajibrahim@rocketmail.com>
ARM: tegra: dvfs: Update Tegra3 display subsystem dvfs tables

Updated 0.95V entries in Tegra3 dvfs tables for display and dsi
with recent characterization results. Removed hdmi and crt dvfs
since characterization allows running these modules at max rate
in the entire supported voltage range.

Bug 817679
Bug 841336

Change-Id: I28651a692e30a20536613460ea0e45155a530af7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107778
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: revjunkie <rajibrahim@rocketmail.com>
ARM: tegra: dvfs: Update Tegra3 I/O dvfs tables

Updated 0.95V entries in Tegra3 dvfs tables for nand, nor, spi, and
pwm clocks with recent characterization results. Removed usb, pcie,
and spdif dvfs since characterization allows running these interfaces
in the entire supported voltage range.

Bug 817679
Bug 841336

Change-Id: Iaaa2a3ff8b3c07915f1cb05e7b14da545428888e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107779
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Signed-off-by: revjunkie <rajibrahim@rocketmail.com>
ARM: tegra: dvfs: Update Tegra3 dsi dvfs tables

Updated entries in Tegra3 dsi dvfs tables with recent characterization results.

Bug 985671.
Bug 1006163.

Change-Id: Ife87f3ccfd9d6147d4aa5b57c1a5750bbabc7e6b
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/112805
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Zu <pzu@nvidia.com>
Signed-off-by: revjunkie <rajibrahim@rocketmail.com>
ARM: Tegra: Enable 900MHz at 1V on restricted pll_m

Allow pll_m to reach 900MHz at 1V on T30, T33, T37
rev A02+ SKUs.

Bug 891320

Change-Id: Idbfb10014ae2a1d06abc3bc1d0bed59c583fac98
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/103453
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Signed-off-by: revjunkie <rajibrahim@rocketmail.com>