Added update to yellow blocks (currently inactive)

When generating a block file, gateways will be incorrectly
named if the user hasn't updated the simulink diagram. This added
(but currently commented out) change forces updates of all the yellow
blocks, by artificially reading and setting one of the yellow block mask
variables.
Updates to shared bram

Added a wrapper so that dual-port rams with asymmetric port widths
are only instantiated when needed, and always correctly identify the
widest port as port A.
Misc fixes to yellow block. Shared bram tested orking on roach2, so far
only for equal port widths (32 bits)
Renamed top module 'top', was 'toplevel'
Exit planahead after run. Change top module name

Added an explicit 'exit' to the planahead tcl script after completion.
Changed planahead bitfile name to 'top', since this is now the name
of the roach2 top module
Updated roach2 test model -- swreg / gpio /bram

Asymmetric port-width shared brams not tested yet.

GPIO / sw_reg / symmetric shared bram working with katcp on Roach2