Updated git ignore to include .swp temp files
Added several simple modules that can be used to test the build system.

dd_dtype, ff_jk and both mux modules should compile and elaborate fine. reg_shift is
currently broken pending investigation.
 On branch dev_ben
 Changes to be committed:

	renamed:    src/rtl/mux.vhd -> mux_2to1.vhd
	new file:   src/rtl/ff_dtype.vhd
	new file:   src/rtl/ff_jk.vhd
	new file:   src/rtl/mux_4to1.vhd
	new file:   src/rtl/reg_shift.vhd
Removed accidental file
Merge pull request #12 from willprice/dev_ben

Merge dev_ben into develop
Added notes to the isa spec
Update isa doc
Update isa_spec.md
Added boolean operations to isa
Merge branch 'feature/isa' of github.com:willprice/vhdl-computer into feature/isa
Tidy line endings
Added arithmetic instructions
Added basic memory access instructions
Update isa_spec.md
Results of pair programming
Merge branch 'feature/isa' of github.com:willprice/vhdl-computer into feature/isa
Add new testbench for the dtype flipflop