Need Testing...

Shifted Stage Tracker, Control Lines.
Added InstructionTestSet.mif and Phase 2 expected input and output excel
(~20Mb)x4versions,,,
Added "WillWriteTo_Memory_H_RF_L" For Writing To Mem in Phase 3...
Just testing.
1.) Registers update at correct times.
2.) Output is not yielding expected values for the given instructions..
DELETED:
1.) OPCodesRev02(11042014)_5.xlsx
2.) F:\Computer
Org\CSC317-Project-1(11-06-2014)d\ProcessorProjectCSC317\Project 1 V
Files\MasterVerilog And MIF PROJECT\simulation

NOTE: PREVIOUS VERSION IS INCOMPLETE (MASTERVERILOG) DID NOT COPY...