diff --git a/simics-workspace/modules/afdxES/pci-register.dml b/simics-workspace/modules/afdxES/pci-register.dml
index f5867ae..bd5e5bf 100644
--- a/simics-workspace/modules/afdxES/pci-register.dml
+++ b/simics-workspace/modules/afdxES/pci-register.dml
@@ -55,10 +55,13 @@ data uint32 count;
 bank pci9056{
     parameter documentation = "Control and Status Register Mapping";
     parameter function = 0;
+    // if the target is 653, make true the byte_order is big-endian
+    // parameter byte_order = "big-endian";
     parameter byte_order = "little-endian";
     parameter register_size = 4;
     parameter partial = true;
-
+    // if the target is 653, make true enable overlapping
+    // parameter overlapping = true;
     register lmisc1 @ 0x000d "Local Miscellaneous Control" {
         parameter hard_reset_value = 0x4;
     }
@@ -159,6 +162,8 @@ bank pci9056{
         }
         field res [7:5] is (reserved);
     }
+    // if the target is 653, make true the size is 4
+    // dmacsr1 size 4 @ 0x00a9 "DMA Channel 1 Command/Status" {
     register dmacsr1 size 1 @ 0x00a9 "DMA Channel 1 Command/Status" {
         field dma1e [0:0] "DMA Channel 1 Enable";
         field dma1s [1:1] "DMA Channel 1 Start" {
@@ -187,8 +192,10 @@ bank pci9056{
         }
         field res [7:5] is (reserved);
     }
-    register loopdmadone size 4 @0x00ac "DMA done";
+
 	register recvdmadone size 4 @0x00b0 "receive DMA done";
+
+    register loopdmadone size 4 @0x00b4 "DMA done";
 }

@@ -199,6 +206,8 @@ data uint32 rm_num;
 bank pciport{
     parameter documentation = "Control and Status Register Mapping";
     parameter function = 1;
+    // if the target is 653, make true the byte_order is little-endian
+    // parameter byte_order = "little-endian";
     parameter byte_order = "big-endian";
     parameter register_size = 4;
     parameter partial = true;
diff --git a/simics-workspace/modules/afdxES/pci-register.dml b/simics-workspace/modules/afdxES/pci-register.dml
index bd5e5bf..581de10 100644
--- a/simics-workspace/modules/afdxES/pci-register.dml
+++ b/simics-workspace/modules/afdxES/pci-register.dml
@@ -4,7 +4,7 @@ import "pci-device.dml";          // Generic PCI device
 import "binary-search.dml";
 import "quick-sort.dml";
 import "log.dml";
-
+extern void LoadCfgTo664Middleware();
 // Basic bank declaration
 bank pci_config {
     // List of base address registers used by the device
@@ -520,6 +520,7 @@ bank pciport{

 	register cfg_done_host @ 0x1004 "cfg_done_host"	{
 		method after_write(memop) {
+			local int ret;
             $is_cfg_done = true;
             call $Print_Cfg_Table();
             switch ($middleware_mode) {
@@ -529,7 +530,15 @@ bank pciport{
                 call $InitVLEnableInfo();
                 break;
             case To664Middleware:
-                call $LoadCfgTo664Middleware();
+				call $ Write_Config_All();
+                LoadCfgTo664Middleware();
+				ret = Init_664_Card();
+				$recv_port_num = get_recv_port_num();
+				if(ret == 0)
+					log "info":"init middle succesee())()())(()())(@@@@@@@@@";
+				else
+					log "info":"init middle failed! ret =%d())()())(()())(@@@@@@@@@",ret;
+				call $Recv_Data_From_664_Middleware_Loop_Event();
                 break;
             default:
                 log "error" : "Unsupported work mode!";
diff --git a/simics-workspace/modules/afdxES/pci-action.dml b/simics-workspace/modules/afdxES/pci-action.dml
index d7ee5b0..faa1f5c 100644
--- a/simics-workspace/modules/afdxES/pci-action.dml
+++ b/simics-workspace/modules/afdxES/pci-action.dml
@@ -40,7 +40,8 @@ method transmit() {
             call $wrapped_frame(buf, length);
             break;
         case To664Middleware:
-            call $Send_Payload_To_664_Middleware(buf, $pciport.tx_port_id.id, $pciport.tx_frame_len.frame_len);
+			Send_To_A664(0, $pciport.tx_port_id.id, buf, $pciport.tx_frame_len.frame_len);
+            //call $Send_Payload_To_664_Middleware(buf, $pciport.tx_port_id.id, $pciport.tx_frame_len.frame_len);
             break;
         default:
             log "error" : "Unsupported work mode";
diff --git a/simics-workspace/modules/afdxES/constant.dml b/simics-workspace/modules/afdxES/constant.dml
index 0549a77..ac4cc11 100644
--- a/simics-workspace/modules/afdxES/constant.dml
+++ b/simics-workspace/modules/afdxES/constant.dml
@@ -82,7 +82,7 @@ constant To664Middleware = 1;

 // for port cache
 constant CACHE_ITEM_MAXSIZE = 10 * 1024;
-constant PORT_CACHE_MAXSIZE = 1024 * 1024;
+constant PORT_CACHE_MAXSIZE =10* 1024 * 1024;

 // for mib
 constant MACA_MIB_CONFIG = 1;
diff --git a/simics-workspace/modules/afdxES/config-tables.dml b/simics-workspace/modules/afdxES/config-tables.dml
index c3ce7ce..34e84c2 100644
--- a/simics-workspace/modules/afdxES/config-tables.dml
+++ b/simics-workspace/modules/afdxES/config-tables.dml
@@ -74,7 +74,30 @@ struct transmit_cfg_ram {
     } ram_data_part3;
 }

+struct transmit_cfg_ram_send{
+	uint32 dst_partition_id;
+	uint32 user_defined_id_l;
+	uint32 user_defined_id_h;
+	uint32 private_ip;
+
+	uint32 vl_id ;
+	uint32 vl_index;
+	uint32 ip_multicast;
+	uint32 min_frame_length;
+	uint32 port_type;
+
+	uint32 partition_id;
+	uint32 interface_id;
+	uint32 protocol_id;
+	uint32 user_defined_id;
+
+	uint32 sub_vl_id;
+	uint32 dest_udp_port;
+	uint32 source_udp_port;
+}
+
 data transmit_cfg_ram transmit_cfg_ram_array[TRANSMIT_CFG_RAM_MAX_SIZE];
+data  transmit_cfg_ram_send transmit_cfg_ram_send_array[TRANSMIT_CFG_RAM_MAX_SIZE];
 data uint32 transmit_cfg_ram_index;
 /////////////////////////////////////  transmit_cfg_ram  end  //////////////////////////////////////
diff --git a/simics-workspace/modules/afdxES/tomiddleware.dml b/simics-workspace/modules/afdxES/tomiddleware.dml
index 378fd67..e2dd1e2 100644
--- a/simics-workspace/modules/afdxES/tomiddleware.dml
+++ b/simics-workspace/modules/afdxES/tomiddleware.dml
@@ -3,9 +3,14 @@ dml 1.2;
 import "port-cache.dml";

 extern int Init_664_Work_Mode(void);
+extern int Init_664_Card(void);
+extern int Send_To_A664(int card_nr, int pord_id, char *buf, int len);
+extern int Recv_From_A664(int card_nr, int port_id, char *buf);
 extern int Send_To_664_Middleware(char *recvbuf, int size);
 extern int Recv_Data_From_664_Middleware(char *sendbuf, int size);
 extern int Recv_Mib_Info_From_664_Middleware(char *recvbuf, int size);
+extern void write_cfg_table(int type ,char *buf, int size);
+extern int get_recv_port_num();

 constant ANALYSE_CFG_CAM = 0;
 constant ANALYSE_CFG_RAM = 1;
@@ -23,97 +28,136 @@ constant PACKET_TX_MIB = 12;
 constant CFG_TYPE_SIZE = 4;
 constant CFG_NUM = 128;

+data int recv_num;

-method Handle_664_Data(uint8 *data, int length) {
+method Handle_664_Data(uint32 port_id,uint8 *data, int length) {
     local bool is_cached_ok;
     local Cache_Item item;
-    local uint32 port_id;

-    memcpy(item.buffer, data+2, length-2);
-    item.size = length - 2;
-    port_id = *cast(&data[1], uint8*);
+    memcpy(item.buffer, data, length);
+    item.size = length ;
+
+	$recv_num++;
+
+	if($recv_num%50 == 0)
+		log "info":"%d ",$recv_num;

-    switch(data[0]) {
-    case PACKET_RECV:
         call $EnPortCache($PortCache[port_id], item) -> (is_cached_ok);
         if (!is_cached_ok) {
             log "error" : "Port: %d's cache has full!\n", port_id;
             ++$rx_buf_overflow_number[port_id];
         }
-        break;
-    case PACKET_MAC_MIB: case PACKET_RX_MIB: case PACKET_TX_MIB:
-        log "error" : "A fatal error， MAC_MIB， RX_MIB， and TX_MIB info cann't recv form this method!\n";
-        break;
-    default:
-        log "error" : "Unsupported frame type!\n";
-        break;
-    }
 }
-
+data int recv_port_num;
 method Recv_Data_From_664_Middleware_Loop_Event() {
     local int length;
     local uint8 *buf = new uint8 [PORT_DATA_SIZE];
-    length = Recv_Data_From_664_Middleware(buf, PORT_DATA_SIZE);
+	local int i;
+	for (i=0; i < $recv_port_num; i++)
+	{
+		length = Recv_From_A664(0, i, buf);

     if (length > 0) {
-        call $Handle_664_Data(buf, length);
+			call $Handle_664_Data(i, buf, length);
+		}
     }

     delete buf;
-    after (0.000001) call $Recv_Data_From_664_Middleware_Loop_Event();
+	//if($load_config_done == 1)
+		after (0.0001) call $Recv_Data_From_664_Middleware_Loop_Event();
+	//else
+	//	after (0.001) call $Recv_Data_From_664_Middleware_Loop_Event();
 }

 method init_middleware_mode() {
+	local int ret;
+	ret = -1;
     if ($middleware_mode == To664Middleware) {
-        Init_664_Work_Mode();
-        call $Recv_Data_From_664_Middleware_Loop_Event();
+     //   Init_664_Work_Mode();
+
         call $Init_Port_Cache();
     }
 }
+data int load_config_done;
+
+method change_tran_cfg(transmit_cfg_ram *transmit_cfg_ram_array, transmit_cfg_ram_send *transmit_cfg_ram_send_array) {
+		transmit_cfg_ram_send_array->dst_partition_id=transmit_cfg_ram_array->ram_data_part4.PARTITION_ID ;
+		transmit_cfg_ram_send_array->user_defined_id_l=transmit_cfg_ram_array->ram_data_part4.USER_DEFINED_ID_L ;
+		transmit_cfg_ram_send_array->user_defined_id_h=transmit_cfg_ram_array->ram_data_part4.USER_DEFINED_ID_H ;
+		transmit_cfg_ram_send_array->private_ip=transmit_cfg_ram_array->ram_data_part4. PRIVATE_IP;
+		transmit_cfg_ram_send_array->vl_id=transmit_cfg_ram_array->ram_data_part1.VL_ID;
+		transmit_cfg_ram_send_array->vl_index=transmit_cfg_ram_array->ram_data_part1.VL_INDEX ;
+		transmit_cfg_ram_send_array->ip_multicast=transmit_cfg_ram_array->ram_data_part1.IP_MULTICAST;
+		transmit_cfg_ram_send_array->min_frame_length=transmit_cfg_ram_array->ram_data_part1.MIN_FRAME_LENGTH ;
+		transmit_cfg_ram_send_array->port_type=transmit_cfg_ram_array->ram_data_part1.PORT_TYPE ;
+		transmit_cfg_ram_send_array->partition_id=transmit_cfg_ram_array->ram_data_part2.PARTITION_ID ;
+		transmit_cfg_ram_send_array->interface_id=transmit_cfg_ram_array->ram_data_part2.INTERFACE_ID ;
+		transmit_cfg_ram_send_array->protocol_id=transmit_cfg_ram_array->ram_data_part2.PROTOCAL_ID ;
+		transmit_cfg_ram_send_array->user_defined_id=transmit_cfg_ram_array->ram_data_part2.USER_DEFINED_ID;
+		transmit_cfg_ram_send_array->sub_vl_id=transmit_cfg_ram_array->ram_data_part3.SUB_VL_ID ;
+		transmit_cfg_ram_send_array->dest_udp_port=transmit_cfg_ram_array->ram_data_part3.DEST_UDP_PORT ;
+		transmit_cfg_ram_send_array->source_udp_port=transmit_cfg_ram_array->ram_data_part3.SOURCE_UDP_PORT ;
+		log "info": "--------------------------------------------";
+			log "info":"dst_partition_id=%x\n",transmit_cfg_ram_send_array->dst_partition_id;
+			log "info":"user_defined_id_l=%x\n",transmit_cfg_ram_send_array->user_defined_id_l;
+			log "info":"user_defined_id_h=%x\n",transmit_cfg_ram_send_array->user_defined_id_h;
+			log "info":"private_ip=%x\n",transmit_cfg_ram_send_array->private_ip;
+			log "info":"vl_id=%x\n",transmit_cfg_ram_send_array->vl_id;
+			log "info":"vl_index=%x\n",transmit_cfg_ram_send_array->vl_index;
+			log "info":"ip_multicast=%x\n",transmit_cfg_ram_send_array->ip_multicast;
+			log "info":"min_frame_length=%x\n",transmit_cfg_ram_send_array->min_frame_length;
+			log "info":"port_type=%x\n",transmit_cfg_ram_send_array->port_type;
+			log "info":"partition_id=%x\n",transmit_cfg_ram_send_array->partition_id;
+			log "info":"interface_id=%x\n",transmit_cfg_ram_send_array->interface_id;
+			log "info":"protocol_id=%x\n",transmit_cfg_ram_send_array->protocol_id;
+			log "info":"user_defined_id=%x\n",transmit_cfg_ram_send_array->user_defined_id;
+			log "info":"sub_vl_id=%x\n",transmit_cfg_ram_send_array->sub_vl_id;
+			log "info":"dest_udp_port=%x\n",transmit_cfg_ram_send_array->dest_udp_port;
+			log "info":"source_udp_port=%x\n",transmit_cfg_ram_send_array->source_udp_port;
+		log "info": "--------------------------------------------";
+}

-method LoadCfgTo664Middleware() {
-    local uint32 data_type = 0;
-    local uint32 cfg_table_size = 0;
-
+method Write_Config_All() {
+	local int data_type;
+	local int cfg_table_size;
+	local int i;
+	local int ret;
+	local int constant_field;
+	local transmit_cfg_ram_send *ram_send;
+	local transmit_cfg_ram *ram;
     data_type = ANALYSE_CFG_CAM;
     cfg_table_size = sizeoftype(analyse_cfg_cam) * CFG_NUM;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
-    Send_To_664_Middleware(cast(&$analyse_cfg_cam_array, uint8*), cfg_table_size);
+	write_cfg_table(data_type,cast(&$analyse_cfg_cam_array, uint8*), cfg_table_size);

     data_type = ANALYSE_CFG_RAM;
     cfg_table_size = sizeoftype(analyse_cfg_ram) * CFG_NUM;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
-    Send_To_664_Middleware(cast(&$analyse_cfg_ram_array, uint8*), cfg_table_size);
+	write_cfg_table(data_type,cast(&$analyse_cfg_ram_array, uint8*), cfg_table_size);

     data_type = TRANSMIT_CFG_RAM;
-    cfg_table_size = sizeoftype(transmit_cfg_ram) * CFG_NUM;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
-    Send_To_664_Middleware(cast(&$transmit_cfg_ram_array, uint8*), cfg_table_size);
+    cfg_table_size = sizeoftype(transmit_cfg_ram_send) * CFG_NUM;
+	for (i=0; i < CFG_NUM; i++) {
+		ram =cast(&($transmit_cfg_ram_array[i]),transmit_cfg_ram *);
+		ram_send =cast(&($transmit_cfg_ram_send_array[i]),transmit_cfg_ram_send *);
+		call $change_tran_cfg(ram, ram_send);
+	}
+	write_cfg_table(data_type,cast(&$transmit_cfg_ram_send_array, uint8*), cfg_table_size);

     data_type = SCHEDULING_CFG_RAM;
     cfg_table_size = sizeoftype(scheduling_cfg_ram) * CFG_NUM;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
-    Send_To_664_Middleware(cast(&$scheduling_cfg_ram_array, uint8*), cfg_table_size);
+	write_cfg_table(data_type,cast(&$scheduling_cfg_ram_array, uint8*), cfg_table_size);

     data_type = RM_CFG_CAM;
     cfg_table_size = sizeoftype(rm_cfg_cam) * CFG_NUM;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
-    Send_To_664_Middleware(cast(&$rm_cfg_cam_array, uint8*), cfg_table_size);
+	write_cfg_table(data_type,cast(&$rm_cfg_cam_array, uint8*), cfg_table_size);

     data_type = RM_CFG_RAM;
     cfg_table_size = sizeoftype(rm_cfg_ram) * CFG_NUM;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
-    Send_To_664_Middleware(cast(&$rm_cfg_ram_array, uint8*), cfg_table_size);
+	write_cfg_table(data_type,cast(&$rm_cfg_ram_array, uint8*), cfg_table_size);

     data_type = FRAGMENT_CFG_RAM;
     cfg_table_size = sizeoftype(fragment_cfg_ram) * CFG_NUM;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
-    Send_To_664_Middleware(cast(&$fragment_cfg_ram_array, uint8*), cfg_table_size);
-
-    data_type = DO_LOAD_CONF;
-    Send_To_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
+	write_cfg_table(data_type,cast(&$fragment_cfg_ram_array, uint8*), cfg_table_size);

-    Recv_Mib_Info_From_664_Middleware(cast(&data_type, uint8*), CFG_TYPE_SIZE);
 }

 method Send_Payload_To_664_Middleware(uint8 *data, uint32 port_id, uint32 length) {
diff --git a/simics-workspace/modules/afdxES/hwa_aes_klib.h b/simics-workspace/modules/afdxES/hwa_aes_klib.h
old mode 100755
new mode 100644
diff --git a/simics-workspace/modules/afdxES/checksum.dml b/simics-workspace/modules/afdxES/checksum.dml
index 1f3a5e8..ce60054 100644
--- a/simics-workspace/modules/afdxES/checksum.dml
+++ b/simics-workspace/modules/afdxES/checksum.dml
@@ -152,7 +152,6 @@ method Reflect(uint64 ref,uint8 ch)->(uint64 value) {
 	}
 }

-// Éú³ÉCRC32 ·­ת±í µڶþÏîÊÇ77073096
 method gen_normal_table(uint32 *table) {
 	local uint32 gx = 0x04c11db7;
 	local uint32 temp;
@@ -191,7 +190,6 @@ method Reverse_Table_CRC(uint8* data, int len, uint32* table)->(uint32 crc_value

 method crc_check(uint8 *data,uint32 size,uint32* table) {
-    /*
 	local uint32 crc = 0xffffffff;
 	local uint32 crc_value;
 	local uint32 crc_value_temp;
@@ -205,11 +203,9 @@ method crc_check(uint8 *data,uint32 size,uint32* table) {
 	STORE_BE32(&crc_value_temp,crc_value);
 	*crc1 = crc_value_temp;
 	log "info": "crc=%x.",*crc1;
-	*/
 }

 method recv_crc_check(uint8 *data,uint32 size,uint32* table)->(bool check) {
-    /*
 	local uint32 old_crc;
 	local uint32 new_crc;
 	local uint32 crc = 0xffffffff;
@@ -236,7 +232,7 @@ method recv_crc_check(uint8 *data,uint32 size,uint32* table)->(bool check) {
 		check = true;
 	else
 		check = false;
-    */
+
     check = true;
 }

diff --git a/simics-workspace/modules/afdxES/queue.dml b/simics-workspace/modules/afdxES/queue.dml
index 1ec7290..692469d 100644
--- a/simics-workspace/modules/afdxES/queue.dml
+++ b/simics-workspace/modules/afdxES/queue.dml
@@ -32,6 +32,7 @@ method DeQueue(Queue *queue, Item *item) {
 		//log "info" : "The fifo is empty";
 	} else {
 		memcpy(item, &(queue->item[queue->front]), sizeoftype(Item)); // 将 queue中的front项存储在结构体中并返回
+		memset(&(queue->item[queue->front]), 0, sizeoftype(Item)); // 将 queue中的front项存储在结构体中并返回
 		queue->front = (queue->front + 1) % ITEM_NUM;
 		--queue->item_num;
 		queue->frame_size -= item->size;
diff --git a/simics-workspace/modules/afdxES2/checksum.dml b/simics-workspace/modules/afdxES2/checksum.dml
index 98f38b5..b26d763 100644
--- a/simics-workspace/modules/afdxES2/checksum.dml
+++ b/simics-workspace/modules/afdxES2/checksum.dml
@@ -192,7 +192,6 @@ method Reverse_Table_CRC(uint8* data, int len, uint32* table)->(uint32 crc_value
 }

 method crc_check(uint8 *data,uint32 size,uint32* table) {
-    /*
 	local uint32 crc = 0xffffffff;
 	local uint32 crc_value;
 	local uint32 crc_value_temp;
@@ -207,11 +206,9 @@ method crc_check(uint8 *data,uint32 size,uint32* table) {
 	STORE_BE32(&crc_value_temp,crc_value);
 	*crc1 = crc_value_temp;
 	log "info": "crc=%x.",*crc1;
-	*/
 }

 method recv_crc_check(uint8 *data,uint32 size,uint32* table)->(bool check) {
-    /*
 	local uint32 old_crc;
 	local uint32 new_crc;
 	local uint32 crc = 0xffffffff;
@@ -236,6 +233,6 @@ method recv_crc_check(uint8 *data,uint32 size,uint32* table)->(bool check) {
     } else {
 		check = false;
     }
-    */
+
     check = true;
 }
diff --git a/simics-workspace/modules/afdxES2/queue.dml b/simics-workspace/modules/afdxES2/queue.dml
index 2e2179e..a095069 100644
--- a/simics-workspace/modules/afdxES2/queue.dml
+++ b/simics-workspace/modules/afdxES2/queue.dml
@@ -32,6 +32,7 @@ method DeQueue(Queue *queue, Item *item) {
 		//log "info" : "The fifo is empty";
 	} else {
 		memcpy(item, &(queue->item[queue->front]), sizeoftype(Item)); // ½« queueÖеÄfrontÏî´洢ÔڽṹÌåÖв¢·µ»Ø
+		memset(&(queue->item[queue->front]), 0, sizeoftype(Item)); // ½« queueÖеÄfrontÏî´洢ÔڽṹÌåÖв¢·µ»Ø
 		queue->front = (queue->front + 1) % ITEM_NUM;
 		--queue->item_num;
 		queue->frame_size -= item->size;
no need
diff --git a/simics-workspace/modules/afdxES/Makefile b/simics-workspace/modules/afdxES/Makefile
index a0fb911..9d20e12 100644
--- a/simics-workspace/modules/afdxES/Makefile
+++ b/simics-workspace/modules/afdxES/Makefile
@@ -9,7 +9,8 @@ SRC_FILES = tomiddleware.c
 DML_FILES = afdxES.dml
 DMLC_FLAGS = -m -I$(SIMICS_WORKSPACE)/include

-MODULE_LDFLAGS = -lws2_32
+MODULE_CFLAGS = -I$(SIMICS_WORKSPACE)/modules/afdxES/inc/
+MODULE_LDFLAGS = $(SIMICS_WORKSPACE)\modules\afdxES\lib\AFDX_Card.lib -lws2_32

 SIMICS_API := 4.6
 THREAD_SAFE := yes
diff --git a/simics-workspace/modules/afdxES/hwa_aes_klib.h b/simics-workspace/modules/afdxES/hwa_aes_klib.h
deleted file mode 100644
index cc3cc62..0000000
--- a/simics-workspace/modules/afdxES/hwa_aes_klib.h
+++ /dev/null
@@ -1,425 +0,0 @@
-#ifndef _HWA_AES_KLIB_H_
-#define _HWA_AES_KLIB_H_
-
-#ifdef WIN32  /* For Windows */
-
-#ifdef _AFDX_EXPORT
-	#ifdef __cplusplus
-		#define _AFDX_DLL_EXPORT extern "C" __declspec(dllexport)
-	#else
-		#define _AFDX_DLL_EXPORT __declspec(dllexport)
-	#endif
-#else
-	#ifdef __cplusplus
-		#define _AFDX_DLL_EXPORT extern "C" __declspec(dllimport)
-	#else
-		#define _AFDX_DLL_EXPORT __declspec(dllimport)
-	#endif
-#endif
-
-#else  /* For VxWorks */
-
-#define _AFDX_DLL_EXPORT
-
-#endif
-
-/* Error Code */
-#define HWA_AES_OK							0
-#define HWA_AES_CARD_NOT_FOUND				-1
-#define HWA_AES_CARD_NOT_OPEN				-2
-#define HWA_AES_CARD_INVALID				-3
-#define HWA_AES_OPEN_FILE_ERR				-4
-#define HWA_AES_AFDX_615A_LOAD_MODE			-5
-#define HWA_AES_RESET_ERR					-6
-#define HWA_AES_XML_FILE_ERR				-7
-#define HWA_AES_PARAMETER_ERR				-8
-#define HWA_AES_SEM_ERR						-9
-#define HWA_AES_CHECK_DMA_TIMEOUT			-10
-#define HWA_AES_BUF_OVERFLOW				-11
-#define HWA_AES_ISR_ERR						-12
-#define HWA_AES_RECV_DATA_ERR				-13
-#define HWA_AES_NO_MEM						-14
-#define HWA_AES_INIT_ERR					-15
-#define HWA_AES_UNKNOWN_ERR					-16
-#define HWA_AES_PORT_EXIST                  -17
-#define HWA_AES_MSGQ_ERR                    -18
-#define HWA_AES_TASK_ERR        			-19
-#define HWA_AES_PHY_ERR          			-20
-#define HWA_AES_PHY_NO_LINK  				-21
-#define HWA_AES_LOAD_FPGA 					-22
-#define HWA_AES_LOAD_XML_FROM_FLASH_MAGICNUM	-23
-#define HWA_AES_LOAD_XML_FORM_FLASH 			-24
-#define HWA_AES_DMA_INIT_ERR 					-25
-#define HWA_AES_SET_PCI_ERR 					-26
-#define HWA_AES_ONLY_NORMAL_MODE 				-27
-#define HWA_AES_CARD_ALREADY_OPEN 				-28
-#define HWA_AES_CARD_CLOSE 						-29
-#define HWA_AES_UNINIT_ERR 						-30
-#define HWA_AES_OPEN_ERR 						-31
-#define HWA_AES_LOAD_XML 						-32
-#define HWA_AES_NOT_SUPPORT 					-33
-#define HWA_AES_CLOSE_ERR 						-34
-#define HWA_AES_PORT_BUSY 						-35
-#define HWA_AES_PORT_NOTFOUND 					-36
-#define HWA_AES_PORT_TOO_MANY					-37
-#define HWA_AES_PORT_DUPLICATE  				-38
-
-
-/*Monitor Mode*/
-#define HWA_AES_MONITOR_START_EXIST -130
-#define HWA_AES_FINISHED_FIND -131
-#define HWA_AES_ONLY_MONITOR_MODE -132
-
-#if 0
-/* MIB statistic : network statistic type */
-#define MIB_CRC_ERR_NUM					0
-#define MIB_SHORT_FRAME_ERR_NUM			1
-#define MIB_LONG_1518_FRAME_ERR_NUM			2
-#define MIB_RECV_FRAME_NUM				3
-#define MIB_RECV_FRAME_64TO127_NUM		4
-#define MIB_RECV_FRAME_128TO255_NUM		5
-#define MIB_RECV_FRAME_256TO511_NUM		6
-#define MIB_RECV_FRAME_512TO1023_NUM	7
-#define MIB_RECV_FRAME_1024TO1518_NUM	8
-#define MIB_RECV_FRAME_BYTES			9
-#define MIB_SEND_FRAME_NUM				10
-#define MIB_SEND_FRAME_64TO127_NUM		11
-#define MIB_SEND_FRAME_128TO255_NUM		12
-#define MIB_SEND_FRAME_256TO511_NUM		13
-#define MIB_SEND_FRAME_512TO1023_NUM	14
-#define MIB_SEND_FRAME_1024TO1518_NUM	15
-#define MIB_SEND_FRAME_BYTES			16
-
-#define MIB_RECV_FRAME_PRE_ERR_NUM 17
-#define MIB_RECV_FRAME_IPCHECKSUM_ERR_NUM 18
-#define MIB_LONG_2048_FRAME_ERR_NUM 19
-
-/*MIB statistic : rx type */
-#define MIB_RX_A_DISABLE_TO_FILTER_FRAME_NUM 0
-#define MIB_RX_B_DISABLE_TO_FILTER_FRAME_NUM 1
-#define MIB_RX_A_CRC_ERR_TO_FILTER_FRAME_NUM 2
-#define MIB_RX_B_CRC_ERR_TO_FILTER_FRAME_NUM 3
-#define MIB_RX_VL_ERR_TO_FILTER_FRAME_NUM 4
-#define MIB_RX_REDUND_ERR_TO_FILTER_FRAME_NUM 5
-#define MIB_RX_DSTUDP_ERR_TO_FILTER_FRAME_NUM 6
-#define MIB_RX_IP_CHECKSUM_ERR_TO_FILTER_FRAME_NUM 7
-#define MIB_RX_IP_LEN_ERR_TO_FILTER_FRAME_NUM 8
-#define MIB_RX_UDP_LEN_ERR_TO_FILTER_FRAME_NUM 9
-#define MIB_RX_IP_FRAGMENT_ERR_TO_FILTER_FRAME_NUM 10
-
-#else
-typedef enum{
-	MIB_TX_SEND_IP_TOTAL_NUM=0,
-	MIB_TX_SEND_UDP_TOTAL_NUM,
-	MIB_TX_SEND_ICMP_TOTAL_NUM,
-	MIB_TX_NR
-}HwaTxMibType;
-
-
-typedef enum{
-	MIB_RX_A_DISABLE_TO_FILTER_FRAME_NUM = 0,
-	MIB_RX_B_DISABLE_TO_FILTER_FRAME_NUM ,
-	MIB_RX_A_SN_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_B_SN_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_VL_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_REDUND_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_DSTPORT_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_IP_CHECKSUM_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_IP_LEN_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_UDP_LEN_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_IP_FRAGMENT_ERR_TO_FILTER_FRAME_NUM ,
-	MIB_RX_BUF_LOST_NUM,
-	MIB_RX_RECIVE_IP_PACKET_TOTAL_NUM,
-	MIB_RX_RECIVE_UDP_PACKET_TOTAL_NUM,
-	MIB_RX_RECIVE_ICMP_PACKET_TOTAL_NUM,
-	MIB_RX_RECIVE_ICMP_BACK_TOTAL_NUM,
-	MIB_RX_RECIVE_ICMP_BACK_LOST_TOTAL_NUM,
-	MIB_RX_RECIVE_ICMP_TLONG_FILTER_NUM,
-	MIB_RX_RECIVE_BUF_BACK_TOTAL_NUM,
-	MIB_RX_NR
-}HwaRxMibType;
-
-
-typedef enum{
-	MIB_CRC_ERR_NUM=0	,
-	MIB_SHORT_FRAME_ERR_NUM	,
-	MIB_LONG_1518_FRAME_ERR_NUM	,
-	MIB_RECV_FRAME_NUM,
-	MIB_RECV_FRAME_64TO127_NUM,
-	MIB_RECV_FRAME_128TO255_NUM,
-	MIB_RECV_FRAME_256TO511_NUM,
-	MIB_RECV_FRAME_512TO1023_NUM,
-	MIB_RECV_FRAME_1024TO1518_NUM,
-	MIB_RECV_FRAME_BYTES,
-	MIB_SEND_FRAME_NUM,
-	MIB_SEND_FRAME_64TO127_NUM,
-	MIB_SEND_FRAME_128TO255_NUM,
-	MIB_SEND_FRAME_256TO511_NUM,
-	MIB_SEND_FRAME_512TO1023_NUM,
-	MIB_SEND_FRAME_1024TO1518_NUM,
-	MIB_SEND_FRAME_BYTES,
-	MIB_RECV_FRAME_PRE_ERR_NUM ,
-	MIB_RECV_FRAME_IPCHECKSUM_ERR_NUM ,
-	MIB_LONG_2048_FRAME_ERR_NUM,
-	MIB_NET_NR
-}HwaNetMibType;
-#endif
-/* data struct */
-typedef enum  /* Afdx Card Work Mode */
-{
-	mode_normal = 0,
-	mode_test,
-	mode_monitor
-}HwaWorkMode;
-
-typedef enum	/* VL Direction*/
-{
-	vl_send	= 0,
-	vl_recv
-}HwaVlDirection;
-
-typedef enum /* Port Type */
-{
-	port_queue	= 0,
-	port_sample,
-	port_sap,
-	port_icmp,
-	port_type_nr
-}HwaPortType;
-
-typedef enum /* Net Type */
-{
-	net_a = 1,
-	net_b ,
-#if HWA_AES_8
-	net_c,
-	net_d,
-	net_e,
-	net_f,
-	net_g,
-	net_h,
-#endif
-	net_ab
-}HwaNetwork;
-
-typedef enum   /* Recv Mode (POLL or Interrupt)*/
-{
-	mode_poll =0,
-	mode_int
-}HwaRecvMode;
-
-typedef enum /* IRIGB Mode*/
-{
-	mode_slave =0 ,
-	mode_master
-}HwaIrigbMode;
-
-typedef enum /* OutPut Select (Rj45 or PMC J4)*/
-{
-	mode_j4=0,
-	mode_rj45
-}HwaOutputMode;
-
-typedef enum  /* Sampling Port Mode (Capture or No Capture)*/
-{
-	mode_nocapure=0,
-	mode_capture
-
-}HwaCaptureMode;
-
-typedef enum   /* Ip muliticast mode */
-{
-	mode_singlecast=0,
-	mode_multicast
-}HwaMulticastMode;
-
-typedef struct 		/* Card Info*/
-{
-	unsigned int vendor_id;
-	unsigned int device_id;
-	unsigned int bus_num;
-	unsigned int slot_num;
-	unsigned int func_num;
-	unsigned int hw_ver;
-	unsigned int work_mode;
-	char serial[16];
-}HwaCardInfo;
-
-typedef struct  /* packet stamp*/
-{
-	unsigned int day;
-	unsigned int hour;
-	unsigned int min;
-	unsigned int sec;
-	unsigned int ms;
-	unsigned int us;
-}HwaTime;
-
-typedef struct    /* recv time*/
-{
-	unsigned int time_low;   /* sec,min,us,ms*/
-	unsigned int time_high;  /* day ,hour*/
-}HwaRecvTime;
-
-typedef struct /* Monitor Mode ,resolved packet info*/
-{
-	unsigned char net;
-	int packet_len;
-	HwaRecvTime time;
-	unsigned int pre_error;
-	unsigned int ip_checksum_error;
-	unsigned int crc_error;
-	unsigned short startbit_pos;
-}HwaPackInfo;
-
-#define HWA_AES_IP_LEN 32
-typedef struct/*sap port information*/
-{
-	unsigned int local_udp;
-	unsigned int remote_udp;
-	char remote_ip[HWA_AES_IP_LEN];
-	HwaRecvTime time;
-	unsigned int network;
-	unsigned int valid;
-}HwaPktSrc;
-
-/* API */
-/* find all card,return the count of card */
-_AFDX_DLL_EXPORT int hwa_aes_find_card (void);
-
-/* free all card resource */
-_AFDX_DLL_EXPORT int hwa_aes_free_card(void);
-
-/* get card info */
-_AFDX_DLL_EXPORT int hwa_aes_get_card_info(int cardnum,HwaCardInfo *card_info);
-
-/* set addr remap ,only for vxworks */
-_AFDX_DLL_EXPORT int hwa_aes_set_addr_map(unsigned int (*func)());
-
-/* set card mode */
-_AFDX_DLL_EXPORT int hwa_aes_set_mode(int cardnum, unsigned int work_mode);
-
-/* open card */
-_AFDX_DLL_EXPORT int hwa_aes_open_card (int cardnum);
-
-/* close card */
-_AFDX_DLL_EXPORT int hwa_aes_close_card (int cardnum);
-
-/* set recv mode (poll or interrupt) */
-_AFDX_DLL_EXPORT int hwa_aes_set_recv_mode(int cardnum,int recv_mode);
-
-/* set irigb mode (slave or master)*/
-_AFDX_DLL_EXPORT int hwa_aes_set_irigb_mode(int cardnum,int irigb_mode);
-
-/* set card output(Rj45 or PMC j4)*/
-_AFDX_DLL_EXPORT int hwa_aes_set_output(int cardnum,int output);
-
-/*Set Caputure Mode*/
-_AFDX_DLL_EXPORT int hwa_aes_set_capture(int cardnum, int caputure);
-
-/*set user id*/
-_AFDX_DLL_EXPORT int hwa_aes_set_user_id(int cardnum,int user_id);
-
-/*load afdx xml*/
-_AFDX_DLL_EXPORT int hwa_aes_load_afdx_config (int cardnum, const char *cfgfilepath);
-
-/*Create VL and Port with Port_name*/
-_AFDX_DLL_EXPORT int hwa_aes_create_afdx_port (int cardnum,char *portName,unsigned int vlDirection,unsigned int *portId);
-
-/*Create VL*/
-_AFDX_DLL_EXPORT int hwa_aes_create_vl (int cardnum,unsigned int vlId,	unsigned int vlDirection,float bag,unsigned int skewMax,unsigned int vlNetwork,unsigned int *vlHandle);
-
-/*Create Port*/
-_AFDX_DLL_EXPORT int hwa_aes_create_port (int cardnum,unsigned int vlId,	unsigned int portType,unsigned short dstUDPPort,unsigned short srcUDPPort,unsigned int vlHandle,unsigned int *portId);
-
-/*Send Afdx Data*/
-_AFDX_DLL_EXPORT int hwa_aes_send (int cardnum,unsigned int portId,unsigned char *pPacket,int len);
-
-/*Receive Afdx Data*/
-_AFDX_DLL_EXPORT int hwa_aes_recv (int cardnum,	unsigned int portId,unsigned char *pPacket,int len,HwaRecvTime *time,unsigned int *network,unsigned int *valid);
-
-/*Receive Afdx Data*/
-_AFDX_DLL_EXPORT int hwa_aes_recv_ex(int cardnum, unsigned int hPort,unsigned char* pPacket, int len,int waittime,HwaPktSrc *pInfo);
-
-/*get port overflow info*/
-_AFDX_DLL_EXPORT int hwa_aes_mib_port_buf_overflow (int cardnum,unsigned int portId, int direction, unsigned int *value);
-
-/*get mib info*/
-_AFDX_DLL_EXPORT int hwa_aes_mib_net_state (int cardnum,HwaNetwork network, HwaNetMibType statType, unsigned int *value);
-
-/*get rx info*/
-_AFDX_DLL_EXPORT int hwa_aes_mib_rx_state (int cardnum,HwaRxMibType statType, unsigned int *value);
-
-/*get tx info*/
-_AFDX_DLL_EXPORT int hwa_aes_mib_tx_state (int cardnum,HwaTxMibType statType, unsigned int *value);
-
-/*clear mib info*/
-_AFDX_DLL_EXPORT int hwa_aes_mib_clear (int cardnum,unsigned int  mask);
-
-/*Close Port*/
-_AFDX_DLL_EXPORT int hwa_aes_close_port(int cardnum,unsigned int portId);
-
-/*resolve time*/
-_AFDX_DLL_EXPORT int hwa_aes_get_time(HwaRecvTime *time,HwaTime *localtime);
-
-/*get software version*/
-_AFDX_DLL_EXPORT int hwa_aes_get_soft_version(unsigned int *version);
-
-/*get hardware version*/
-_AFDX_DLL_EXPORT int hwa_aes_get_hard_version(int cardnum,unsigned int *version);
-
-/*get firmware version*/
-_AFDX_DLL_EXPORT int hwa_aes_get_firmware_version(int cardnum,unsigned int *version);
-
-/*check phy state*/
-_AFDX_DLL_EXPORT int hwa_aes_get_phystate(int cardnum,unsigned int *pState);
-
-/* Monitor Mode*/
-
-/*Monitor mode,start recv*/
-_AFDX_DLL_EXPORT int hwa_aes_monitor_start_recv(int cardnum);
-
-/*Monitor mode,stop recv*/
-_AFDX_DLL_EXPORT int hwa_aes_monitor_stop_recv(int cardnum);
-
-/*Monitor mode ,reslove packet*/
-_AFDX_DLL_EXPORT int hwa_aes_packet_find_next(unsigned char* pRecvBuff,int nSize,unsigned char ** ppPacket,HwaPackInfo* pPacketInfo,unsigned char** pCurPacketPos);
-
-/*creat a sap prot*/
-_AFDX_DLL_EXPORT int hwa_aes_create_sap_port(int cardNum,char *portName,unsigned int vlDir,unsigned int Udp,unsigned int subVl,unsigned int *portID);
-
-/*send AFDX data by a sap port*/
-_AFDX_DLL_EXPORT int hwa_aes_sap_send(int cardNum,unsigned int portId,unsigned char *buf,unsigned int bufLen, HwaPktSrc sapInfo);
-
-/*receive AFDX data from a sap port*/
-_AFDX_DLL_EXPORT int hwa_aes_sap_recv(int cardNum,unsigned int portId,unsigned char *buf,unsigned int bufLen,int waittime,HwaPktSrc *sapInfo);
-
-/*delete a sap port*/
-_AFDX_DLL_EXPORT int hwa_aes_close_sap_port(int cardNum,unsigned int portId);
-
-/*creat an ICMP port*/
-_AFDX_DLL_EXPORT int hwa_aes_create_icmp(int cardNum,char * portName,unsigned int vlDir,unsigned int * portID);
-
-/*send AFDX data by an ICMP port*/
-_AFDX_DLL_EXPORT int hwa_aes_icmp_send(int cardnum,unsigned int portId,unsigned char * buf,int bufLen,char *dstIp);
-/*recv AFDX data from an ICMP port */
-_AFDX_DLL_EXPORT int hwa_aes_icmp_recv(int cardnum,unsigned int portId,unsigned char * pPacket,int len,int waittime,HwaPktSrc *sapInfo);
-
-/*delete an ICMP port*/
-_AFDX_DLL_EXPORT int hwa_aes_close_icmp(int cardNum,unsigned int portId);
-
-/*read FPGA register*/
-_AFDX_DLL_EXPORT unsigned int hwa_aes_reg_read(int cardnum,unsigned int addr,int dev);
-
-/*write FPGA register*/
-_AFDX_DLL_EXPORT unsigned int hwa_aes_reg_write(int cardnum,unsigned int addr,unsigned int value,int dev);
-
-_AFDX_DLL_EXPORT  int hwa_aes_set_local_time(int cardnum,HwaTime *localtime);
-
-
-_AFDX_DLL_EXPORT  int hwa_aes_get_local_time(int cardnum,HwaTime *localtime);
-
-_AFDX_DLL_EXPORT void hwa_aes_get_soft_build_version(char *version);
-
-
-#endif
add afdxES card header
add afdxES card lib
add RDC
diff --git a/simics-workspace/modules/afdxES/tomiddleware.c b/simics-workspace/modules/afdxES/tomiddleware.c
index 5033e43..2f57c79 100644
--- a/simics-workspace/modules/afdxES/tomiddleware.c
+++ b/simics-workspace/modules/afdxES/tomiddleware.c
@@ -1,6 +1,17 @@
 #include "tomiddleware.h"

 SOCKET client_socket;
+#define MAX_RECV_PORTS 128
+#define MAX_SEND_PORTS 128
+#define MAX_PACK_LEN 8192
+
+SOCKET client_socket;
+static unsigned send_ports[MAX_SEND_PORTS];
+static unsigned recv_ports[MAX_RECV_PORTS];
+static int send_port_num;
+static int recv_port_num;
+static char send_port_name[30]="send_port_";
+static char recv_port_name[30]="recv_port_";

 int Init_664_Work_Mode(void) {
     WSADATA wsa;
@@ -86,3 +97,275 @@ int Recv_Mib_Info_From_664_Middleware(unsigned char *recvbuf, int size) {
     }
     return len;
 }
+
+const int analyse_cfg_cam_array_len = MAX_RECV_PORTS;
+struct analyse_cfg_cam analyse_cfg_cam_array[MAX_RECV_PORTS];
+
+const int analyse_cfg_ram_array_len = MAX_RECV_PORTS;
+struct analyse_cfg_ram analyse_cfg_ram_array[MAX_RECV_PORTS];
+
+const int transmit_cfg_ram_array_len = MAX_SEND_PORTS;
+struct transmit_cfg_ram transmit_cfg_ram_array[MAX_SEND_PORTS];
+
+const int scheduling_cfg_ram_array_len = MAX_SEND_PORTS;
+struct scheduling_cfg_ram scheduling_cfg_ram_array[ MAX_SEND_PORTS];
+
+const int fragment_cfg_ram_array_len = MAX_SEND_PORTS;
+struct fragment_cfg_ram fragment_cfg_ram_array[MAX_SEND_PORTS];
+
+const int rm_cfg_cam_array_len = MAX_VLS;
+struct rm_cfg_cam rm_cfg_cam_array[MAX_VLS];
+
+const int rm_cfg_ram_array_len = MAX_VLS;
+struct rm_cfg_ram rm_cfg_ram_array[MAX_VLS];
+
+void write_cfg_table(int type ,unsigned char *buf, int size) {
+
+	switch(type){
+		case ANALYSE_CFG_CAM:
+				memcpy(analyse_cfg_cam_array,buf,size);
+				break;
+		case ANALYSE_CFG_RAM:
+				memcpy(analyse_cfg_ram_array,buf,size);
+				break;
+		case TRANSMIT_CFG_RAM:
+				memcpy(transmit_cfg_ram_array,buf,size);
+				break;
+		case SCHEDULING_CFG_RAM:
+				memcpy(scheduling_cfg_ram_array,buf,size);
+				break;
+		case RM_CFG_CAM:
+				memcpy(rm_cfg_cam_array,buf,size);
+				break;
+		case RM_CFG_RAM:
+				memcpy(rm_cfg_ram_array,buf,size);
+				break;
+		case FRAGMENT_CFG_RAM:
+				memcpy(fragment_cfg_ram_array,buf,size);
+				break;
+		default:
+			break;
+	}
+}
+
+static int all_zeroes(char *buf, int buf_len)
+{
+	for (int i = 0; i < buf_len; i++)
+		if (buf[i] != 0)
+			return 0;
+	return 1;
+}
+
+static char* port_type_string(u16 port_type)
+{
+	switch (port_type) {
+	case 0:
+		return "Queue";
+	case 1:
+		return "Sample";
+	case 2:
+		return "SAP";
+	case 3:
+		return "ICMP";
+	default:
+		printf( "port_type_string(): unrecognized port type.\n");
+		return "";
+	}
+}
+
+static char* ab_enable_string(u32 enable_a, u32 enable_b)
+{
+	if (enable_a && enable_b)
+		return "AB";
+	else if (enable_a)
+		return "A";
+	else if (enable_b)
+		return "B";
+	else
+		printf( "ab_enable_string(): at least one of network a/b must be enabled.\n");
+	return "";
+}
+
+
+void send_port_string(FILE *fp) {
+	int i;
+	int j;
+	u64 tt;
+	for (i = 0; i < transmit_cfg_ram_array_len; i++) {
+		struct transmit_cfg_ram *ram = &transmit_cfg_ram_array[i];
+		if (all_zeroes((char *)ram, sizeof(*ram)))
+			continue;
+		send_port_num++;
+		sprintf(send_port_name,"send_port_%d",i);
+		fprintf(fp,"<AFDXPort ");
+		fprintf(fp,"BAG=\"%d\" ",scheduling_cfg_ram_array[ram->vl_index].bag / 1000);
+		fprintf(fp,"DirectionType=\"Send\" ");
+		fprintf(fp,"DstIP_2=\"%d\" ",ram->user_defined_id_h<<6|ram->user_defined_id_l>>8);
+		fprintf(fp,"DstIP_3=\"%d\" ",ram->user_defined_id_l & 0xff);
+		fprintf(fp,"DstIP_4=\"%d\" ",ram->dst_partition_id);
+		fprintf(fp,"DstUDP=\"%d\" ",ram->dest_udp_port);
+		fprintf(fp,"MaxFrameSize=\"%d\" ",fragment_cfg_ram_array[i].max_frame_length);
+		fprintf(fp,"MinFrameSize=\"%d\" ",ram->min_frame_length);
+		fprintf(fp,"Multicast=\"%s\" ",ram->ip_multicast? "Enable" : "Disable");
+		fprintf(fp,"PartitionID=\"%d\" ",ram->partition_id);
+		fprintf(fp,"PortName=\"%s\" ",send_port_name);
+		fprintf(fp,"PortNetwork=\"%s\" ",ab_enable_string(ram->interface_id & 1, ram->interface_id & 2));
+		fprintf(fp,"PortType=\"%s\" ", port_type_string(ram->port_type));
+		fprintf(fp,"SrcUDP=\"%d\" ",ram->source_udp_port);
+		fprintf(fp,"SubVL=\"%d\" ",ram->sub_vl_id);
+		fprintf(fp,"VL=\"%d\" ",ram->vl_id);
+		fprintf(fp,"VLNetwork=\"%s\" ",ab_enable_string(ram->interface_id & 1, ram->interface_id & 2));
+		fprintf(fp,"/>\n");
+	}
+}
+
+struct rm_cfg_ram* get_vl_conf(u16 vl_id)
+{
+	for (int i = 0; i < rm_cfg_cam_array_len; i++)
+		if (rm_cfg_cam_array[i].vl_id == vl_id)
+			return &rm_cfg_ram_array[rm_cfg_cam_array[i].address];
+	return NULL;
+}
+
+static unsigned ip_part(u32 ip, unsigned offset)
+{
+	return (unsigned)((unsigned char *)&ip)[offset - 1]; // NOTE: offset is 1-based.
+}
+
+void recv_port_string(FILE *fp) {
+	int i;
+	for (i = 0; i < analyse_cfg_cam_array_len; i++) {
+
+		struct analyse_cfg_cam *cam = &analyse_cfg_cam_array[i];
+		struct analyse_cfg_ram *ram = &analyse_cfg_ram_array[cam->address];
+		if (all_zeroes((char *)cam, sizeof(*cam)) || all_zeroes((char *)ram, sizeof(*ram)))
+			continue;
+
+		recv_port_num++;
+		struct rm_cfg_ram *vl_ram = get_vl_conf(cam->vl_id);
+		sprintf(recv_port_name,"recv_port_%d",i);
+		fprintf(fp,"<AFDXPort ");
+		fprintf(fp,"DirectionType=\"Recv\" ");
+		fprintf(fp,"DstIP_2=\"%d\" ",ip_part(cam->dest_ip, 3));
+		fprintf(fp,"DstIP_3=\"%d\" ",ip_part(cam->dest_ip, 2));
+		fprintf(fp,"DstIP_4=\"%d\" ",ip_part(cam->dest_ip, 1));
+		fprintf(fp,"DstUDP=\"%d\" ",cam->dest_udp);
+		fprintf(fp,"IntegralityCheckA=\"%s\" ",vl_ram->network_a_ic_enable? "Enable" : "Disable");
+		fprintf(fp,"IntegralityCheckB=\"%s\" ",vl_ram->network_b_ic_enable? "Enable" : "Disable");
+		fprintf(fp,"Multicast=\"%s\" ",cam->multicast_id? "Enable" : "Disable");
+		fprintf(fp,"PartitionID=\"%d\" ",ip_part(cam->dest_ip, 1));
+		fprintf(fp,"PortName=\"%s\" ",recv_port_name);
+		fprintf(fp,"PortNetwork=\"%s\" ",ab_enable_string(ram->network_a_enable, ram->network_b_enable));
+		fprintf(fp,"PortType=\"%s\" ",port_type_string(ram->port_type));
+		fprintf(fp,"Redund=\"%s\" ",vl_ram->rm_enable?  "Enable" : "Disable");
+		fprintf(fp,"SkewMax=\"%d\" ",vl_ram->skew_max);
+		fprintf(fp,"SrcUDP=\"0\" ");
+		fprintf(fp,"VL=\"%d\" ",cam->vl_id);
+		fprintf(fp,"VLNetwork=\"%s\" ",ab_enable_string(vl_ram->network_a_enable, vl_ram->network_b_enable));
+		fprintf(fp,"/>\n");
+	}
+}
+
+void LoadCfgTo664Middleware() {
+	FILE *fp;
+	fp = fopen("a664conf.xml","w+");
+	if(fp == NULL){
+		printf("open rx_mib.txt failed\n");
+	} else {
+		printf("open rx_mib.txt succeed\n");
+	}
+
+	fprintf(fp,"<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n");
+	fprintf(fp,"<AFDXCard CreateTime=\"2011-12-27 13:39:29\" Company=\"Hwa Create\">\n");
+	fprintf(fp,"<AFDXNetwork Speed=\"100\">\n");
+//	fprintf(fp,"<AFDXEs UserDefinedID=\"%d\">\n",transmit_cfg_ram_array[0].user_defined_id_h<<14 | transmit_cfg_ram_array[0].user_defined_id_l);
+	fprintf(fp,"<AFDXEs UserDefinedID=\"%d\">\n",transmit_cfg_ram_array[0].user_defined_id);
+	send_port_string(fp);
+	recv_port_string(fp);
+	fprintf(fp,"</AFDXEs>\n");
+	fprintf(fp,"</AFDXNetwork>\n");
+	fprintf(fp,"</AFDXCard>\n");
+
+	fclose(fp);
+}
+
+int Init_664_Card(void) {
+	int cardnum;
+	int card_count;
+	int ret =0;
+	int i;
+
+
+	//find card
+	card_count = hwa_aes_find_card();
+	if (card_count <= 0) {
+		printf("No Card : %d\n", card_count);
+		hwa_aes_free_card();
+		getchar();
+		return -1;
+	}
+	//for test
+	cardnum = 0;
+
+	hwa_aes_set_mode(cardnum,mode_normal);
+
+	//open card
+	printf("Opening Card...\n");
+	if ((ret=hwa_aes_open_card(cardnum)) != HWA_AES_OK) {
+		printf("open failed\n");
+		getchar();
+		return ret;
+	}
+	printf ("open card OK!\n");
+
+	//load config
+	printf("load afdx config ...\n");
+	if( (ret=hwa_aes_load_afdx_config (cardnum, "a664conf.xml")) != HWA_AES_OK)	{
+		printf ("load afdx config failed with %d!\n",ret);
+		getchar();
+		return -4;
+	}
+	printf ("load afdx config OK!\n");
+
+	for (i=0; i < send_port_num; i++) {
+		sprintf(send_port_name,"send_port_%d",i);
+		if((ret=hwa_aes_create_afdx_port(cardnum,send_port_name,vl_send,send_ports+i)) != HWA_AES_OK) {
+			printf ("create send port error\n");
+			getchar();
+			if(i==0)
+				return 100;
+			return i;
+		}
+	}
+	for (i=0; i < recv_port_num; i++) {
+		sprintf(recv_port_name,"recv_port_%d",i);
+		if((ret=hwa_aes_create_afdx_port(cardnum,recv_port_name,vl_recv,recv_ports+i)) != HWA_AES_OK) {
+			printf ("create recv port error\n");
+			getchar();
+			return -8;
+		}
+	}
+
+	return 0;
+}
+
+int Recv_From_A664(int card_nr, int port_id, unsigned char *buf) {
+	HwaRecvTime time;
+	unsigned network;
+	unsigned valid;
+
+	int len = hwa_aes_recv(card_nr, recv_ports[port_id], buf, MAX_PACK_LEN, &time, &network, &valid);
+
+	return len;
+}
+
+int Send_To_A664(int card_nr, int port_id, unsigned char *buf, int len) {
+	int ret = hwa_aes_send (card_nr, send_ports[port_id], buf, len);
+
+	return ret;
+}
+
+int get_recv_port_num() {
+	return recv_port_num;
+}
+
diff --git a/simics-workspace/modules/afdxES/tomiddleware.h b/simics-workspace/modules/afdxES/tomiddleware.h
index 4d82b19..896f819 100644
--- a/simics-workspace/modules/afdxES/tomiddleware.h
+++ b/simics-workspace/modules/afdxES/tomiddleware.h
@@ -1,5 +1,6 @@
 #ifndef __TOMIDDLEWARE_H__
 #define __TOMIDDLEWARE_H__
+#pragma once

 #include <stdio.h>
 #include <string.h>
@@ -7,7 +8,97 @@
 #include <errno.h>
 #include <unistd.h>
 #include <WINSOCK2.H>
+#include "hwa_aes_klib.h"

+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+
+#define  MAX_RECV_PORTS  128
+#define MAX_SEND_PORTS  128
+#define MAX_VLS  128
+
+struct analyse_cfg_cam {
+	u32 address;
+
+	u32 multicast_id : 1;
+	u32 icmp_type_id : 1;
+	u32 __reserved : 30;
+
+	u32 dest_ip;
+
+	u16 dest_udp;
+	u16 vl_id;
+};
+
+struct analyse_cfg_ram {
+	u16 port_type : 2;
+	u16 network_a_enable : 1;
+	u16 network_b_enable : 1;
+	u16 __reserved : 12;
+};
+
+struct transmit_cfg_ram {
+	u32 dst_partition_id;
+	u32 user_defined_id_l;
+	u32 user_defined_id_h;
+	u32 private_ip;
+
+	u32 vl_id ;
+	u32 vl_index;
+	u32 ip_multicast;
+	u32 min_frame_length;
+	u32 port_type;
+
+	u32 partition_id;
+	u32 interface_id;
+	u32 protocol_id;
+	u32 user_defined_id;
+
+	u32 sub_vl_id;
+	u32 dest_udp_port;
+	u32 source_udp_port;
+};
+
+struct scheduling_cfg_ram {
+	u32 bag;
+};
+
+struct rm_cfg_cam {
+	u32 address;
+	u16 vl_id;
+};
+
+struct rm_cfg_ram {
+	u32 network_a_enable : 1;
+	u32 network_b_enable : 1;
+	u32 network_a_ic_enable : 1;
+	u32 network_b_ic_enable : 1;
+	u32 rm_enable : 1;
+	u32 skew_max : 21;
+	u32 vl_enable : 1;
+	u32 __reserved : 5;
+};
+
+struct fragment_cfg_ram {
+	u16 max_frame_length;
+};
+
+enum netpack_type_t {
+	ANALYSE_CFG_CAM = 0,
+	ANALYSE_CFG_RAM = 1,
+	TRANSMIT_CFG_RAM = 2,
+	SCHEDULING_CFG_RAM = 3,
+	RM_CFG_CAM = 4,
+	RM_CFG_RAM = 5,
+	FRAGMENT_CFG_RAM = 6,
+	PACKET_SEND = 7,
+	PACKET_RECV = 8, // the only pack from midware to simulator.
+	DO_LOAD_CONF = 9,
+	MAC_MIB = 10,
+	RX_MIB = 11,
+	TX_MIB = 12
+};

 extern int Init_664_Work_Mode(void);
 extern int Send_To_664_Middleware(unsigned char *recvbuf, int size);
diff --git a/simics-workspace/modules/ARINC-429Mode/ARINC_429Mode.py b/simics-workspace/modules/ARINC-429Mode/ARINC_429Mode.py
old mode 100644
new mode 100755
index c4d67ac..3dece5c
--- a/simics-workspace/modules/ARINC-429Mode/ARINC_429Mode.py
+++ b/simics-workspace/modules/ARINC-429Mode/ARINC_429Mode.py
@@ -1,40 +1,41 @@
-# MODULE: ARINC-429Mode
-# COMPONENT: ARINC_429Mode
-
-# empty_component.py - sample code for a Simics configuration component
-# Use this file as a skeleton for your own component implementations.
-
-from comp import *
-
-class ARINC_429Mode(StandardConnectorComponent):
-    """The empty component class."""
-    _class_desc = "empty component"
-    _help_categories = ()
-
-    def setup(self):
-        StandardConnectorComponent.setup(self)
-        if not self.instantiated.val:
-            self.add_objects()
-
-    def add_objects(self):
-        # TODO: replace the example pci-bus connector with relevant connectors
-        self.add_connector('pci', PciBusUpConnector(0, 'sample_dev'))
-        # TODO: create relevant conf_objects and set initial attributes in them
-        clock = self.add_pre_obj('clock', 'clock', freq_mhz = 10)
-        sample = self.add_pre_obj('sample_dev', 'sample_pci_device')
-        sample.int_attr = 4711
-
-    # TODO: replace attribute with relevant attributes
-    class attribute0(ConfigAttribute):
-        """attribute0"""
-        attrtype = "i"
-        def _initialize(self):
-            self.val = 4711
-        def getter(self):
-            return self.val
-        def setter(self, val):
-            self.val = val
-
-    # TODO: replace attribute with relevant attributes
-    class attribute1(SimpleConfigAttribute(None, 'i')):
-        """attribute1"""
+# MODULE: ARINC_429Mode
+# COMPONENT: ARINC_429Mode
+
+# empty_component.py - sample code for a Simics configuration component
+# Use this file as a skeleton for your own component implementations.
+
+from comp import *
+
+class ARINC_429Mode(StandardConnectorComponent):
+    """The empty component class."""
+    _class_desc = "empty component"
+    _help_categories = ()
+
+    def setup(self):
+        self.add_connector('pci_bus', PciBusUpConnector(0, 'afdxES'))
+        afdxES = self.add_pre_obj('afdxES', 'afdxES')
+        afdxES2 = self.add_pre_obj('afdxES2', 'afdxES2')
+        RDC = self.add_pre_obj('RDC', 'RDC')
+        afdxES2.RDC = RDC
+        RDC.ARINC664_2 = afdxES2
+        RDC.LoadCfg = afdxES2
+        afdxES.phyA = afdxES2
+        afdxES2.phyA = afdxES
+        afdxES.phyB = afdxES2
+        afdxES2.phyB = afdxES
+
+    def add_objects(self):
+        self.add_connector('pci_bus', PciBusUpConnector(0, 'afdxES'))
+        afdxES = self.add_pre_obj('afdxES', 'afdxES')
+
+    class component_connector(Interface):
+        def get_check_data(self, cnt):
+            return []
+        def get_connect_data(self, cnt):
+            return [[[0, self._up.get_slot('afdxES')]]]
+        def check(self, cnt, attr):
+            return True
+        def connect(self, cnt, attr):
+            self._up.get_slot('afdxES').pci_bus = attr[1]
+        def disconnect(self, cnt):
+            self._up.get_slot('afdxES').pci_bus = None
\ No newline at end of file
diff --git a/simics-workspace/modules/ARINC-664Mode/ARINC_664Mode.py b/simics-workspace/modules/ARINC-664Mode/ARINC_664Mode.py
old mode 100644
new mode 100755
index 912391d..430dd9b
--- a/simics-workspace/modules/ARINC-664Mode/ARINC_664Mode.py
+++ b/simics-workspace/modules/ARINC-664Mode/ARINC_664Mode.py
@@ -1,40 +1,34 @@
-# MODULE: ARINC-664Mode
-# COMPONENT: ARINC_664Mode
-
-# empty_component.py - sample code for a Simics configuration component
-# Use this file as a skeleton for your own component implementations.
-
-from comp import *
-
-class ARINC_664Mode(StandardConnectorComponent):
-    """The empty component class."""
-    _class_desc = "empty component"
-    _help_categories = ()
-
-    def setup(self):
-        StandardConnectorComponent.setup(self)
-        if not self.instantiated.val:
-            self.add_objects()
-
-    def add_objects(self):
-        # TODO: replace the example pci-bus connector with relevant connectors
-        self.add_connector('pci', PciBusUpConnector(0, 'sample_dev'))
-        # TODO: create relevant conf_objects and set initial attributes in them
-        clock = self.add_pre_obj('clock', 'clock', freq_mhz = 10)
-        sample = self.add_pre_obj('sample_dev', 'sample_pci_device')
-        sample.int_attr = 4711
-
-    # TODO: replace attribute with relevant attributes
-    class attribute0(ConfigAttribute):
-        """attribute0"""
-        attrtype = "i"
-        def _initialize(self):
-            self.val = 4711
-        def getter(self):
-            return self.val
-        def setter(self, val):
-            self.val = val
-
-    # TODO: replace attribute with relevant attributes
-    class attribute1(SimpleConfigAttribute(None, 'i')):
-        """attribute1"""
+# MODULE: ARINC_664Mode
+# COMPONENT: ARINC_664Mode
+
+# empty_component.py - sample code for a Simics configuration component
+# Use this file as a skeleton for your own component implementations.
+
+from comp import *
+
+class ARINC_664Mode(StandardConnectorComponent):
+    """The empty component class."""
+    _class_desc = "empty component"
+    _help_categories = ()
+
+    def setup(self):
+        StandardConnectorComponent.setup(self)
+        if not self.instantiated.val:
+            self.add_objects()
+
+    def add_objects(self):
+        self.add_connector('pci_bus', PciBusUpConnector(0, 'afdxES'))
+        afdxES = self.add_pre_obj('afdxES', 'afdxES')
+        afdxES.middleware_mode = 1
+
+    class component_connector(Interface):
+        def get_check_data(self, cnt):
+            return []
+        def get_connect_data(self, cnt):
+            return [[[0, self._up.get_slot('afdxES')]]]
+        def check(self, cnt, attr):
+            return True
+        def connect(self, cnt, attr):
+            self._up.get_slot('afdxES').pci_bus = attr[1]
+        def disconnect(self, cnt):
+            self._up.get_slot('afdxES').pci_bus = None
del myhello
del rtc_module