vhdlpp: Subprogram class inherits from ScopeBase.
vhdlpp: Added ScopeBase::transfer_from() method.
vhdlpp: Support for variable declarations in subprograms.

Fixes sorrymsg: "variable_declaration not supported."
vhdlpp: Support for std_logic_vector return type in functions.

VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
vhdlpp: Workaround to avoid translation of variables to wires in functions.
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
Merge pull request #45 from orsonmmz/subprogram

Subprograms