mdp: mdss: Tune bandwidth and clock based on ROI

Calculate bandwidth and MDP clock requirement considering
the ROI submitted for a frame. When doing partial frame update
for smart panels, the data actually fetched for a pipe is not
always the full resolution of the buffer programmed. Use the
ROI passed to find out the region of fetching and calculate the
bandwidth and clock values accordingly.

Change-Id: I01f24f8fd9a42a2c4d705b8eb0a7658e79884175
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
msm: mdss: Do not program DSI PLL registers from DSI controller

MDSS DSI driver currently programs certain DSI PLL registers as
part of the DSI PHY off sequence. This is incorrect and could
lead to some unexpected errors such as DSI PLL getting turned off
while the branch clocks are still on. Fix this by removing all
such register programming.

Change-Id: Ie1e88cd18de6b8ef8804f7a2b34b8b8282166c96
CRs-Fixed: 509801
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
msm: mdss: add a separate register region for DSI PHY

The DSI PHY register offset from the controller base is
different for different targets. So, add a separate register
region for DSI PHY in the device tree. This register base and
offset will be used to access the DSI PHY registers. Also
change the register offsets which are dependent on the
controller base address.

Change-Id: Ie1d08950f3c8c8801908a1b3cf7db46a44b4e8c3
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>