verilator_tb_utils: change all 'times' to uint64_t

Franck Jullien reported that unsigned long is not a valid argument
for tfp->dump() on 32-bit machines.
This changes all 'time' (cycles, really) references to uint64_t.
cores: add mt46v16m16p DDR memory model

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add wb_altera_ddr_wrapper

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add ps2 core

This core is originally from opencores, but have been rewritten
in verilog and had a lot of bugfixes added to it.
Due to this, it makes more sense to add this as a whole core
instead of pulling in the original and adding the complete rewrite
as a patch.
systems: add atlys board port

OpenRISC system for Digilent Atlys development board.
Basically lifted 'as is' from the orpsocv2 port at:
git://git.openrisc.net/stefan/orpsoc

TODO:
 - Rewrite dvi_gen (currently a hacked up Xilinx whitepaper)
 - Clean up the Xilinx MIG memory controller wrapper
   (and possibly generate the MIG with coregen on fly)
 - General cleanup and de-orpsocv2-fication
Merge pull request #48 from skristiansson/verilator_tb_utils

verilator_tb_utils: change all 'times' to uint64_t
Merge branch 'atlys' of git://github.com/skristiansson/orpsoc-cores
Add wb_ram

wb_ram is a generic memory that is intended to map against on-chip RAM or registers
wb_ram: Fix broken link in README.md
or1200-generic: add debug tap anf jtag_vpi support

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add csrbrg core
cores: add minimac2 core
Merge branch 'minimac2' of https://github.com/veprbl/orpsoc-cores into upstream
verilator_tb_utils: add a JTAG server for OpenOCD

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
or1200-generic: use jtagServer from verilator_tb_utils

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
systems/atlys: set MMU sets to 128

There's room for the extra logic/RAM resources this takes,
so no reason to skimp on it.
mor1kx-generic: add debug tap and jtag server support

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
atlys/clkgen: remove defparams
atlys: remove invalid DIVIDE(2) on BUFIO

Newer ISE (reported on >= 14.5) fail to build designs with
BUFIO2 that has the DIVIDE parameter set to 2.
The error message is:
"ERROR:PhysDesignRules:2502 - Issue with pin connections and/or
configuration on
   block:<dvi_gen0/sysclk_div>:<BUFIO2_BUFIO2>.  BUFIO2 has an invalid
setting
   of DIVIDE by 2. This setting is not supported. For more information
please
   see Answer Record 56113.
ERROR:Pack:1642 - Errors in physical DRC."

And, Answer Record 56113 states the following:
"In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can
occasionally enter a stuck state. Hence, it is not supported and an
alternative implementation needs to be used."

To get around this, instead of feeding the 100 MHz system clock
into dvi_gen, an already divided by 2 50MHz clock is used.
atlys: add timing constraints for dvi_gen CDC