adi_project : ZC706 board name changed on 2014.2
daq1 : Update project to 2014.2

  - Cores are upadted
  - Concat module does not swap output anymore
  - Clock signal name ps7_clk_* changed to clk_fpga_*
axi_ad9234: axi_ad9680 copy
fmcadc3: daq2 copy
fmcadc3: initial updates
2014.2 updates
daq1: clean up dma interfaces
fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems
ultrasound: disconnected ADN4670 chips from SPI lines.

Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
usdrx1: Updated project to 2014.2
ad9265: Initial commit
AD9434: Initial check in of the library and project with ZC706
common: Initial check in of ad_serdes_in.v

A generic serdes module for input interface, support both 6 and 7 series.
ad_serdes_in: Update the serdes_in module

Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
ad9434: Merge the ad9434_if interface data outputs into one single bus
ad9434: Fix the adc to dma interface.

All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
ad9434: Fix the processor read interface

Fix the processor read interface, preventing to have nets with multiple drivers. Made a few cosmetic changes in the code too.
ad9434: Fix SPI line physical constraints

SPI lines are not differential.
ad9434: Fix adc_clk constraint

ADC clock is 500 Mhz.