Initial check-in of reworked arm interrupt routines.

Main things to note on this branch:
* spl routines are inlined, less complex, and small (kernel drops in size)
* interrupts are handled in priority order (for most things it doesn't
  matter, but pending ipls are used to determine if there is any work to do)
* arm_irqhandler.c is derived from footbridge_irqhandler.c, which was based
  on work by thorpej.
* The code tries to touch hardware as little as possible.
* spl masks are no longer tracked, as the system is based on pending ipls

The shared code uses global ipl lists to track which interrupt handlers
are attached to which ipl (arm_iplq[]).

Interrupt sources register with the common code to indicate:
* how many irq lines they have
* a function to set the hardware mask.
* call arm_intr_claim and arm_intr_disestablish to setup handlers

When an interrupt occurs the ipl is flagged as pending, in ipls_pending.
If it can be handled at the current_ipl_level the code does so.
If it can't be handled it's left until the current_ipl_level drops.

As the ipl level changes down a quick test is made of the new ipl level
against the ipls_pending value.  If an ipl is pending arm_intr_splx_lifter
is called to handle the pending ipls.

It should be noted that all interrupts are left enabled at the hardware
level, interrupts are only masked when they occur.  They are only
re-enabled after it's interrupt handler is called.  Hardware masks are not
changed at any other time.

Soft interrupts are treated the same as hardware interrupts, they
register as a provider, and do not get treated specially.  All the soft
interrupt handlers are placed onto the relevant global ipl queue, the same
as hard interrupts handlers.

At the moment only footbridge within a cats has been updated to use the new
handling.

Todo:
* change the handling of interrupts, so that the hardware doesn't register
  a routine to fetch the hardware status.  Instead is makes a call which
  provides the mask.  This removes the primary flag when registering an
  interrupt provider.  It also makes more sense with multiple interrupt
  sources.
* Arm v5 has the clz asm, which could be used instead of the carefully
  hand rolled arm_intr_fls function.
* switch cats isa support to use this framework.
* switch iomd and acorn32 to use this framework.
* switch shark to use this framework.
* port any other arm platforms that are interested
* examine overlaps between this code and ppcoea-renovation branch.
* add support for different trigger types (Edge, level, pulse, etc)

(note that iomd and shark currently touch hardware on every spl change,
hence why they're targets to port)
Switch footbridge isa to use common code.  This required changes to the
arm code:
* intr_claim now takes a type to indicate edge, level or pulse. It has
  isa level understanding of types and uses a callback to set the hardware
  type.
* slightly adjust how pending interrupts are queued up.
* switch the ICU setup code to make use the defines in i8259reg.h, rather
  than using magic numbers.
Rework registration call, so that it no longer takes a status paramater.

Rework dispatch routines, so no implicit ordering is required in the irq
groups.  This removes the primary flag, and also makes hardware dependant
dispatch routines again.

Update arm_intr_queue_irqs to disable interrupts.  This is necessary when
child buses are present, eg isa bus, as the isa interrupt handler is
called with interrupts enabled, and I believe that the footbridge handler
was trampling on the isa handler setting up pending flags.

cats can now install using the update irq code (previously it would
randomly hang)
Sync with HEAD
Fix off by one issues when deciding if there are ipls which can be
processed from splx.

Don't lower the spl level in raisespl.

Correct test when scheduling a interrupt.

These issues were more noticable on slower (EB7500ATX) than on faster
(cats) hardware.  Particularly noticed when handling disk interrupts,
where disk interrupts were processed even when spl was splbio. They
should have been blocked till the next splx.  This was causing disk
timeouts.

Add futher diagnostic output from arm_intr_print_pending_irq_details.
Add some temporary code used to debug the problem. To be remove later.
Sync with HEAD.
Make branch build again following sync to head.
Sync to HEAD.
Rename some structures, eg intrq->intrline, irqgroup->pic.  A lot of
member variables have changed name to reflect this.

Change the API for registering a PIC with the common code, so that it
passes a structure to the common code, rather than lots of parameters.
Fix merge botch.
Sync to HEAD.
Add initial reworking of acorn32 to use new interrupt code.

Note that cats probably won't work currently as acorn32 changed the way
that the pic is registered, it has to provide the irq lines as on acorn32
we attach the iomd after we need to register irqs for the pioc.  So we
setup the irqs for iomd before malloc etc are available.  This needs
to be fixed.

More work is still needed to update most of the podulebus drivers.
First I need to add podulebus wrapper for interrupts that handles the
maskaddr and maskbits.   Exposing them to the common irq code is wrong.
Revert rpc_machdep.c to last version.  The changes in it for kinetic should
be in HEAD and then pulled up, by reverting the changes from the branch it
should make the pull up simpler.
Sync to HEAD.
Fixup vidcvideo, current_spl_level is replaced with current_ipl_level.
Fix acorn32 to boot.  Also fix cpu.h, a change sneaked in that isn't
currently being used.
Make sure interrupts are not lost between comparing the pending ipl list
and the updating of the current_ipl_level.

Also bias the comparision so that the "fast path" is to assume that we're
unlikely to have interrupts to process on the splx call.
Reorder splx code so we don't have to disable interrupts, we might get a
few spurious times when we go into splx_lifter, but that'll hopefully be
the minority case.

Uses suggested reordering from scw@
We now that we're turning on and off the interrupts, so don't store the
previous state (which will be interrupts disabled)
Fix up footbridge code to work with changed arm_intr_register.

Cats now boots again.