created scons tool for coregen
created scons tool for xst
moved coregen options from coregen tool to SConstruct
improved handling of coregen options, enforce generation of .v file inside Coregen builder
fixed: target of XstRun did not actually depend on HDL files. also removed .prj file as target, instead it is generated as NamedTemporaryFile
figure out verilog/vhdl by extension
added database of FPGA boards and used it for coregen_options and xst_options
cosmetic changes, added TODOs
reordered/reformatted SConstruct, create -sd dynamically, fix wrong description in coregen builder
added more devices
cosmetic changes in coregen options
cleaned up xst options, device.xst_options returns {"p": value} instead of value
renamed XstRun -> XstSynthesis
added ngdbuilder tool, some minor other changes
protect against missing ngdbuild_options
added map tool
replace_path/replace_suffix/get_suffix functions from util.py call str on their filename arguments, making it possible to directly pass File objects instead of str(File)
added PAR tool, modified MAP tool to work with PAR (same file suffixes...)
cleaned up file suffixes in MAP and PAR
allow intstyle in xst_options (although it is more of a "meta-option")