counter_out was removed such that counter_logic is returning a single value.

// File: counter_d.v
// Generated by MyHDL 0.9dev
// Date: Mon Jun  2 14:32:31 2014

`timescale 1ns/10ps

module counter_d (
    cnt,
    clk,
    ena,
    rst,
    updown,
    step,
    MIN_COUNT,
    MAX_COUNT
);

output [15:0] cnt;
reg [15:0] cnt;
input clk;
input ena;
input rst;
input [15:0] updown;
input step;
input [8:0] MIN_COUNT;
input [15:0] MAX_COUNT;

always @(posedge clk) begin: COUNTER_D_COUNTER_LOGIC
    if ((rst == 1)) begin
        cnt <= 0;
    end
    else if ((ena == 1)) begin
        if ((updown == 1)) begin
            if (($signed({1'b0, cnt}) == ($signed({1'b0, MIN_COUNT}) - 1))) begin
                cnt <= 0;
            end
            else begin
                cnt <= (cnt + step);
            end
        end
        else begin
            if ((cnt == (MIN_COUNT + 1))) begin
                cnt <= MAX_COUNT;
            end
            else begin
                cnt <= (cnt - step);
            end
        end
    end
    cnt <= cnt;
end

endmodule