VL (broken): change functions/tasks to have regular portdecls rather than taskports
clean up Verilog-2005 functions/tasks
vl: mostly fix stuff for new fundecl format
first cut at systemverilog function parsing
vl: fix a couple more things
Merge with sol
fix up parser tests and writer for new function parsing stuff
vl: fix check for wrong type of port type in xf-expand-functions
merge
vl: apply sizing to function declarations
minor patch, get systests working again
add some test of new function stuff
Extended support for SystemVerilog functions (with Sol)

  - New task/function representation: use real portdecls instead
    of the old "taskport" structures

  - New support for parsing SystemVerilog functions, including
    ports with data types like "logic [3:0]", multiple statements
    in their bodies, etc.

  - Updated existing transforms to deal with the new representation

  - Added some extended tests