use mode default when synthesizing module whose name matches the value of options.top
added -D foo=bar for verilog defines
use mode default when synthesizing module whose name matches the value of options.top
version 14.12.3
uart kc705 example from Suhas
removed reference to user.tcl
uart_fpgamake -> uart_kc705
fix call to $(realpath )
write logic_location file when writing bitstream
fix typo in ll generation option
logic_location_file does not take a parameter
Preliminary support for Altera compilation

This commit added some preliminary support for Altera FPGAs.
It also includes an example to compile the UART example.
Renaming: changed variable and scripts name as suggested by Jamey
Merge pull request #1 from hanw/master

Add preliminary support for Altera FPGAs
fixed echo fpgamake.mk <target>
Merge tag 'v14.12.4' into ubuntu

Conflicts:
	fpgamake
	tcl/Makefile.fpgamake.common
updated to 14.12.4