Adding latest fft_core.ngc file from Rurik
Fixed problem in network/eth/{0..4}/we_decode

The previous version used the least significant bit of the XID in an attempt to
send half the channels to one RX FIFO and half to the other.  The problem with
that is that the two LSbs of the XID are constant for a given 10 GbE interface!
Thus, each interface always wrote to its "even" FIFO or always to its "odd"
FIFO.

The problem was further compounded because only the "odd" FIFO from the "eth3"
interface is used to decide when to start reading out buffered FIFO data to
feed the X engines.  If the eth3 interface always wrote to the "even" FIFO (and
never to the "odd"), then data (and sync) would never be fed to the X engine.
If that interface always wrote to the "odd" FIFO (and never to the "even"),
data would get fed to the X engine, but not sync because the sync only comes
from the "even" FIFO (the "odd" FIFO's sync is discarded because it should
never be given SOWF packets).

I fixed this by using bit 2 of the XID to determine which FIFO to write to.
Bit 2 of the XID is the least significant bit that is not constant for a given
link in direct connect mode.

I also added some diagnostic registers and changed the simulink names (but not
tcpborphserver names) of others.  Here is a summary of the new and/or changed
network related registers (plus the network/control register which did NOT
change):

network/ctrl - [UNCHANGED] Control register for network related logic.

ctrl[31] = 10 GbE Core Reset
ctrl[30] = RX FIFO Reset
ctrl[5]  = Network TX Enable
ctrl[4]  = Network RX Enable
ctrl[0]  = Bypass control (0=normal; 1=bypass)

network/pcnt - [NEW] Packet count register for network receive FIFOs.  Each
interface has two FIFOs.  The packet count goes up every time an "end of frame"
word is written to the FIFO.  The count goes down every time a "end of frame"
word is read out of the FIFO.  The FIFOs are 16 packets deep.  Readout starts
when the "eth3 pcnt1" (i.e. the packet count of eth3's "odd" FIFO) reaches 4 (I
think).

pcnt[03:00] = eth0 pcnt0
pcnt[07:04] = eth0 pcnt1
pcnt[11:08] = eth1 pcnt0
pcnt[15:12] = eth1 pcnt1
pcnt[19:16] = eth2 pcnt0
pcnt[23:20] = eth2 pcnt1
pcnt[27:24] = eth3 pcnt0
pcnt[31:28] = eth3 pcnt1

network/sowf/cnt0
network/sowf/cnt1
network/sowf/cnt2
network/sowf/cnt3 - [NEW] Received Start of Walsh Frame counters for each
interface.  The "RX FIFO Reset" bit (network/ctrl[30]) resets the counters.

cnt0 is count of SOWF rising edges recevied on eth0
cnt1 is count of SOWF rising edges recevied on eth1
cnt2 is count of SOWF rising edges recevied on eth2
cnt3 is count of SOWF rising edges recevied on eth3

network/xid - [NEW] 8 least significant bits of the received XIDs on each
interface all in one 32 bit register.

xid[07:00] = eth0 xid[7:0]
xid[15:08] = eth1 xid[7:0]
xid[23:16] = eth2 xid[7:0]
xid[31:24] = eth3 xid[7:0]

network/mcnt/rx - [NEW] 8 least significant bits of the received MCNTs on each
interface all in one 32 bit register.

rx[07:00] is 8 LSbs of mcnt received on eth0
rx[15:08] is 8 LSbs of mcnt received on eth1
rx[23:16] is 8 LSbs of mcnt received on eth2
rx[31:24] is 8 LSbs of mcnt received on eth3

network/mcnt/rx0
network/mcnt/rx1
network/mcnt/rx2
network/mcnt/rx3 - [RENAMED] 32 least significant bits of the received MCNTs on
each interface (register per interface).  These used to be called
network/mcnt_rx0 etc.  I don't think the name change will affect tcpborphserver
names.

rx0 is 32 LSbs of mcnt received on eth0
rx1 is 32 LSbs of mcnt received on eth1
rx2 is 32 LSbs of mcnt received on eth2
rx3 is 32 LSbs of mcnt received on eth3

network/mcnt/tx - [RENAMED] 32 least significant bits of the transmitted MCNT.
This used to be called network/mcnt_tx.  I don't think the name change will
affect tcpborphserver names.

tx is 32 LSbs of transmitted mcnt
Fix offset in network/eth/re_control slice block

The slice block was labeled "b7" and bit 7 is definitely the desired bit, but
the slice block used an LSB offset of 2 instead of 7.  Probably a copy/paste
error.  Now it is set to 7.
Add .gitignore
Fix off-by-one bug in net rx fifo readout

The fix is to remove the delay block in network/eth/re_control.  This delay was
intended to match the latency of the counter, but it turns out that matching
the latency caused the initial relo output pulse to be one clock cycle shorter
than desired.  This initial one-clock-cycle-short relo pulse caused the data to
be shifted by one cycle forever after.  Removing this delay made things behave
as expected.
Capture network SOWF bit with first data word only

The SOWF bit from the packet header is high for all words of a sync packet.
Capturing it in the RX FIFOs with each 64-bit data word meant that it would be
toggling on the output of the RX FIFOs since they readout the data in 32-bit
"half words".  This can lead to problems of determining the "real" SOWF bit
downstream.  To fix this, we only capture the SOWF bit with the first 64 bit
data word of a sync packet.
Enable net RX FIFOs only after SOWF rising edge

If the RX FIFOs were enabled when the SOWF bit high (i.e. during the reception
of a sync packet), only a portion of the first packet would be written to the
FIFOs.  This would throw off the readout logic which expects only complete
packets to be written to the FIFOs.  The fix is to enable to write enables only
on the first rising edge of SOWF (after the "RX enable" bit is set in the
control register) rather than on any high cycle of SOWF.
Move EOF bit to low half of net RX words

The EOF (end of frame) bit is asserted with the last 64 bit word of the packet.
The network RX FIFOs store the SOWF and EOF bits alongside the data.  These two
bits of metadata need two extra bits of padding on the FIFO inputs since the
readout side of the FIFOs is only 32 bits wide.  The FIFO input used to be
constructed as:

SOWF, EOF, data[63:32], 2'b00, data[31:0]

The above arrangement associates both SOWF and EOF with the upper (i.e. first)
half of the 64-bit data word.  This is correct for SOWF, but EOF is really
associated with the lower (i.e. last) half of the 64-bit data word.  The new
arrangement is:

SOWF, 1'b0, data[63:32], 1'b0, EOF, data[31:0]
Fix Goto tags in network/eth/N blocks

This was leftover from incomplete modifications after some copy/paste
operations (copying network/eth/0 to network/eth{1..3}).  The "ethtweak"
function in the newly added "ethtweak.m" file can be used to fix these up in
the future.
Strip sync and EOF from "other" antenna

This ensures that only one sync pulse per walsh frame is sent to the X engine
(rather than one sync pulse per antenna per walsh frame).
Double the rate of SOWF generated for the network

The SOWF pulses generated for the network packets were half the desired rate
(i.e. one pulse for every two Walsh frames).  This doubles the rate to one SOWF
pulse for every Walsh frame.
[sma_corr] Updated the Shared BRAM and snapshot blocks to their newer mlib_devel versions.

Could not get this to compile without timing errors though.
Updated library links to mlib_devel commit 182fd40
Move some sma_corr InitFcn code to PreLoadFcn

This causes the model setup code to run just before the model is loaded to
ensure that variables that various blocks depend on will be defined.

In order to make the find_system calls that remain in InitFcn run faster,
SearchDepth parameters have been added to them.
Update CASPER blocks to mlib_devel version 5697c23

Also change sample time for xeng/Step block (a simulink block, not a xilinx
block) to match its downstream Gateway In block (in the SW Reg block).
First sma_corr with switch based corner turner!
Changed latency of sb_state shared BRAM to 3

Changed the latency of the sma_corr/xengine/final_acc/sb_state BRAM and the
corresponding delay blocks above it to 3 to fix timing problems in the latest
build.
Change latency of sma_corr/xengine/xeng_vg/dataN

Increase the latency of these 8 shared BRAMs from 1 to 3.  Also update the
corresponding delay block to latency 3 as well.  Hopefully this will ease
timing further.
Revert "[sma_corr] Updated the Shared BRAM and snapshot blocks to their newer mlib_devel versions."

This reverts commit c4e50e461503d00be63bcc81c19970ff05092a5e.
Merge branch 'davidm' into rprimian