initial Verilog harness implementation
Merge branch 'master' of https://github.com/ucb-bar/chisel into vtests
fix signal partitioning
add ROM & Mem initiailization
polish shadow names
add mem shadows
add comments
exclude reset
add VPD dump for --debug
generate API interpreter only with --test
change vpd extension
fix the reset prob: all tests pass!
support multi resets
support multi clocks
not generate shadows for bindings and undeclared ports
polish multi clock support
add set_clocks api
Merge branch 'master' of https://github.com/ucb-bar/chisel into vtests
clean up
more clean up