[FIX] Add reset sequence for a proper cold reset

This change includes the latest version of the altera-pll which has
been generated with the MegaFunction Wizard, the ResetSequencer IP-Core,
the adaption of the DDR3-SDRAM Controller settings and some minor
changes in the toplevel.vhd file

Change-Id: I44c9d273d4fa4c8c2f3633171c40c4e171a5eb39
[TASK] Clean up C5 SoC Quartus design files

- Replace tabs by spaces
- Remove trailing spaces

Change-Id: I0c7904572c04a2142a98885ba8c0bfb73c19e631
[FIX] Remove unused pin from toplevel design

Change-Id: I096a45860e6dc513a34b57885b87206ac930919d
[FIX] Connect missing reset in C5 SoC Qsys

Change-Id: I6b5460a653114b60c2329c19698851e8771f4dd1
[FIX] Remove signal tap relicts from qsf

Change-Id: Ieefaddbfa57d840ec50e7c5427e4c6c8be9eb89d