Commonization of RCC clock enable / reset for entire STM32 family

Commonization commit for L1 F1 F2 F3 and F4 to be compatible with F0

Currently only for F4 target as tested example. I can extend and test it for F1 and L1 target, for F2 i cannot test (having no discovery platform for F2)

Let's see on the current standard, shown in next example. If I would like to create the line of code, I must open the Reference Manual and search for appropriate bit and register.

```C
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_USART1EN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN);
....
rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_USART1RST);
rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_USART1RST);
```

After my patch, i can write more readable code, because bit and register selection can be done in the background in rcc.c 

```C
rcc_periph_clock_enable(RCC_USART1);
rcc_periph_clock_enable(RCC_GPIOD);
....
rcc_periph_reset_pulse(RST_USART1)
```


Regards.

   Frantisek Burian

(Compatibility with old method preserved)