cappuccino/lsu: let stores go through to dcache when disabled

In case the cache is temporarily disabled, stores to cache hits
still have to be performed in to the cache.
decode: do not generate illegal insn exception on l.msync

l.msync is a class II instruction, which means that it is
optional to implement.
However, this doesn't mean that the instruction should
generate an illegal instruction exception when it's not
implemented, instead the arch spec states that it should
instead be implemented as a no-op on implementations
that has strongly ordered memory accesses.

To be consistent, parameters are added for all three
sync instructions, l.msync, l.psync and l.csync.
None of them have actual implementations, and l.psync and
l.csync will generate illegal insn exceptions when their
parameters are defined as "NONE".
cappuccino/lsu: perform stores to cache during cache inhibit

To keep the cache memory coherent under the situation
where a system writes to a cache-inhibit memory area
while the dmmu is on, but reads from it when it is off,
writes have to go through to the cache in case of a hit.
mor1kx v2.2