Register directory && WIP register file
Instantiate register file and signals
Tweak register file values
tests registers 0 and 1
Merge branch 'register-directory-and-files' of github.com:dmpro2014/fpga into register-directory-and-files
Update tests to new interface
Tests for id high/low
Add constant write signal && more stuff
Test id readonly
Tests for address registers
Merge branch 'register-directory-and-files' of github.com:dmpro2014/fpga into register-directory-and-files
Test for register file
Move clk_period declaration
Partially working test
Tests fixed, also merge