Add .ctags files to exclude test data
verilog: Ignore preprocessor macros in module port declaration

Support the following port declarations:

module mod (
    `ifdef DEF
    input wire a,
    `else
    input wire b,
    `endif
    output wire c
    );
Merge pull request #194 from vhda/verilog/fix-macros-in-portdecl

verilog: Ignore preprocessor macros in module port declaration
c, d: wchar_t is not a keyword

C: See ISO/IEC 9899:201x 6.4.1.
D: See http://dlang.org/lex#Keyword
ant: add "build.xml" as a pattern

"build.xml" is the default input file name for ant.

Signed-off-by: Masatake YAMATO <yamato@redhat.com>
ant: add a pattern for picking a name of property as a tag

Signed-off-by: Masatake YAMATO <yamato@redhat.com>
Units, ant: use ant parser for build.xml.

Signed-off-by: Masatake YAMATO <yamato@redhat.com>
Units, ant: add missing args.ctags to use Ant parser

Signed-off-by: Masatake YAMATO <yamato@redhat.com>
Merge pull request #196 from b4n/c/wchar_t-handling

c, d: wchar_t is not a keyword
Merge pull request #192 from ffes/dot-ctags

Add .ctags files to exclude test data
core: Update program name, url and copyright date
core: Remove references to fishman-ctags

* Update links to Github organization instead of fishman area.
* Replace references to fishman with exuberant.
core: Add development area pseudo tag
docs: Cleanup documentation

* Remove first and second-person sentences, replacing them with proper
  third-person sentences.
* Replaced double-colon with a single colon.
* Commented out some sentences, specifically parts prefixed with TODO.

Please note the following:

1. English is not my natural language, so please re-review everything.
2. optlib description is very complex:
   * Could it be simplified?
   * Can we move it to a new document specific for it?