[DRIVERS] Use vmm_inb and vmm_outb to access uart

Since on x86 UART is IO mapped, vmm_in_8 et all won't
work on x86. Change the access to vmm_inb which uses
I/O space instructions on x86 and does MMIO on other
architectures.

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[x86] Make serial port as default console.

Make serial port as the default console for x86.
It can be overridden to use STDIO by having
console=stdio in the command line.

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[x86] Fix compilation and Enable 8250 code.

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[x86] HPET: BUG_ON on single try is overkill

Makes sense especially with HPET to retry for few times.

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[x86] Paged real mode page tables and some more intercepts.

o Added 32-bit shadow pagetable support (only adding entries)
  for guest booting in paged real mode.
o Guests registers set to point to the reset vector so that
  bios loaded at a specified address maps correctly to which
  xvisor will get page faults in paged real mode.
o Added some more intercepts viz CRn read/write (enable them).

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[x86] Minor Fix: Change uncontional print to a debug log.

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[x86] Remove svm launch file and make things inline

Since vmsave/vmrun, non of them, don't save any
GPRs except for RAX, the launcher function needs
to save it. Passing multiple arguments to a seperate
function doesn't make sense to inlined the complete
svm_launch in svm_run.

Signed-off-by: Himanshu Chauhan <hschauhan@nulltrace.org>
[ARM] arm32ve: Don't trap advanced SIMD instructions for Guest

The VFP virtualization already takes care of SIMD instructions
because SIMD instructions uses VFP data registers which are
saved/restored by VFP virtualization.

This patch disables trapping of advance SIMD instructions for
arm32ve port.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Add inline macros for reading feature registers

The reading macros for feature registers were missing for arm32ve
port hence this patch.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Print complete state for normal VCPUs

This patch enables printing entire register state (including
VFP state) on character device for normal VCPUs.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: Print hypervisor context for normal VCPUs

It will be useful to print hypervisor context in arch_vcpu_regs_dump()
for debugging purposes hence this patch.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm64: Support printing of complete state for normal VCPU

This patch does improvements to  cpu_vcpu_helper, cpu_vcpu_sysregs,
and cpu_vcpu_vfp. It primarily adds support for printing complete
state for normal VCPU to a character device.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Support printing of complete state for normal VCPU

This patch adds support of printing complete state for normal VCPU
to a character device.

Signed-off-by: Anup Patel <anup@brainfault.org>
Merge remote-tracking branch 'upstream/master' into A20
[ARM] arm32ve: Minor improvements to VFP save/restore

Current, VFP save/restore were directly checking HCPTR value programmed
in HW. This means arch_vcpu_switch() will have to restore HCPTR value
before doing VFP restore which can lead to bugs in-future. This patch
updates VCPU save/restore to check HCPTR value from private context
instead of HW.

Signed-off-by: Anup Patel <anup@brainfault.org>
arm32ve: Add support for CP14 ThumbEE virtualization

ThumbEE, Debug, and Trace support are part of CP14 hence it becomes
important for us to provide infrastructure for virtualizing CP14
register accesses.

This patch adds basic infrastructure for CP14 virtualization and uses
it for virtualizing ThumbEE registers.

All CP14 accesses from VCPU always trap into hypervisor hence for
ThumbEE virtualization we do following:
1. CP14 read access: We return value read from HW on behalf VCPU
and save a copy of it VCPU private context.
2. CP14 write access: We write value to HW and also save a copy of
it in VCPU private context.
3. CP14 save: We don't need to explicitly save registers because
we already keep track of all CP14 read/write accesses via traps.
4. CP14 restore: We have to explicitly restore all register values
by updating them in HW.

Signed-off-by: Sting Cheng <sting.cheng@gmail.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm64: Minor improvements to VFP save/restore

Currently, VFP save/restore were directly checking CPTR_EL2 value
programmed in HW. This means arch_vcpu_switch() will have to restore
CPTR_EL2 value before doing VFP restore which can lead to bugs
in-future. This patch updates VCPU save/restore to check CPTR_EL2
value from private context instead of HW.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm64: Improve ThumbEE virtualization

The arm64 port already had ThumbEE virtualization. This patch makes
arm64 ThumbEE virtualization in-line with arm32ve port.

Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32: Add support for CP14 ThumbEE virtualization

The ARMv7 processors have ThumbEE extensions which can be used
by Java or Dalvick based root filesystems such as Android.

ThumbEE, Debug, and Trace support are part of CP14 hence it becomes
important for us to provide infrastructure for virtualizing CP14
register accesses.

This patch adds basic infrastructure for CP14 virtualization and uses
it for virtualizing ThumbEE registers.

All CP14 accesses from VCPU always trap into hypervisor hence for
ThumbEE virtualization we do following:
1. CP14 read access: We return value read from HW on behalf VCPU
and save a copy of it VCPU private context.
2. CP14 write access: We write value to HW and also save a copy of
it in VCPU private context.
3. CP14 save: We don't need to explicitly save registers because
we already keep track of all CP14 read/write accesses via traps.
4. CP14 restore: We have to explicitly restore all register values
by updating them in HW.

Please note that the CP14 virtuatization added by this patch in an
adapted from arm32ve port.

Signed-off-by: Sting Cheng <sting.cheng@gmail.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
[ARM] arm32ve: arm64: Fix cpu_vcpu_coproc for instruction emulation

The ARM instruction emulation library under arch/arm/cpu/common uses
cpu_vcpu_coproc provided by arm32, arm32ve, and arm64 to determing
coprocessor callbacks.

This patch fixes cpu_vcpu_coproc for arm32ve and arm64 because we now
have CP14 read/write functions available in both these ports.

Signed-off-by: Anup Patel <anup@brainfault.org>