Merge pull request #7 from wallento/or1k

Significant changes in or1k libgloss and newlib
or1k: add support for l.swa/l.lwa atomic instructions

This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.

A couple of fixes to typos in nearby/related code are also snuck
into this.

cpu/
	* or1korbis.cpu (h-atomic-reserve): New hardware.
	(h-atomic-address): Likewise.
	(insn-opcode): Add opcodes for LWA and SWA.
	(atomic-reserve): New operand.
	(atomic-address): Likewise.
	(l-lwa, l-swa): New instructions.
	(l-lbs): Fix typo in comment.
	(store-insn): Clear atomic reserve on store to atomic-address.
	Fix register names in fmt field.

opcodes/
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Likewise.
	* or1k-opc.c: Likewise.
	* or1k-opc.h: Likewise.
	* or1k-opinst.c: Likewise.
or1k: Correct mask for exception handling

During exception handling we determine the actual exception by using
the program counter which was stored during the preamble at the
exception entry, e.g. 0x844 etc. This is the parameter to the
function. The shifting spared 2 positions to directly use the number *
4 for addressing in the vectors. But to do this properly (see
0x844>>6=0x21 instead of 0x20), we need to mask the lower 8 bits.
or1k: Add multicore identifier SPR

 * Add the multicore identification register as proposed at system
   register group, address 14.
 * Add or1k_coreid() function for convenience

Add number of cores
Synchronization functions
WIP: Multicore support
or1k: Remove references to malloc from libgloss
or1k: Add mmu_init function
or1k: Fixes in interrupt handler

 * r9 has changed in branch delay slot, save it to stack before jalr

 * Copy and paste error for table base addresses
or1k: Make or1k_interrupt_handler standard

Register or1k_interrupt_handler as standard exception handler on
interrupts.