Implement a few more vector aarch64 insns:
LD1 {vT.4s}, [xN|SP], #16
ADD Dd, Dn, Dm
SUB Dd, Dn, Dm
SMIN Vd.T, Vn.T, Vm.T
UMIN Vd.T, Vn.T, Vm.T
SMAX Vd.T, Vn.T, Vm.T
UMAX Vd.T, Vn.T, Vm.T
SMINV Vd.T, Vn.T, Vm.T
UMINV Vd.T, Vn.T, Vm.T
SMAXV Vd.T, Vn.T, Vm.T
UMAXV Vd.T, Vn.T, Vm.T
DUP Vd.T, Rn
FADD/FSUB/FMUL/FDIV32x4



git-svn-id: svn://svn.valgrind.org/vex/trunk@2812 8f6e269a-dfd6-0310-a8e1-e2731360e62c