Remove the notion of multiple dests for an instruction.

The code was littered with single-dest assumptions.  If we end up
needing multiple dests, we can revisit this or introduce special
cases.

Here are some possibilities of where this might come up:

- Any x86-32 function call produces a result in a scratch register (if
  non-void) and destroys the other scratch registers.  This is
  currently modeled by a Kill pseudo-instruction that comes right
  after the lowered Call instruction.

- On x86-32, calling an I64 function returns its result in edx:eax.
  This can probably be handled similar to the Kill instruction.

- A sincos intrinsic mapped to a single machine instruction produces
  two usable results.  We might define the sincos instruction to
  return the sin result, then add a special instruction to materialize
  the cos result.

- The x86-32 IMUL instruction multiplies two 32-bit values and creates
  a 64-bit result in edx:eax.  A 32-bit multiply would take the result
  from eax and add a Kill instruction for edx.  However, if we
  implement 64-bit multiplication in terms of 32-bit IMUL, we need to
  use edx as well.  As above, we could add a special instruction to
  materialize the high 32-bit portion.

- Currently FLAGS are not explicitly modeled.  We assume no
  instruction reordering except for placement of assignments for phi
  lowering, and we assume these assignments do not affect the flags.
  Implementing scheduling or other non-trivial instruction reordering
  will require a redesign.