Disable (possibly) non-deterministic test

It appears that the symbol we choose to mangle may be chosen
non-deterministically. Eliminate the output comparison test until we
resolve this.
Merge branch 'master' of https://github.com/ucb-bar/chisel
add try/catch block to try to diagnose NullPointerException.
Revert "Merge branch 'master' of https://github.com/ucb-bar/chisel"

This reverts commit 226efb483c3157f80604c93cbf95d664b4fea661, reversing
changes made to 85f837c9fe8927020c8ca1572ecf0b8470f9344c.
change flo format to use ' for width, remove widths from ops that don't need them, and add widths to literals
merge
Merge commit 'f64fb987de5c09272f976c9656a3ea5314274544'

add try/catch block to try to diagnose NullPointerException.
Use LinkedHashMap if map is iterated over

Iterating over HashMaps is not deterministic.
change output to flo
revive comments in Counter.scala
make counter signals visible without --debug option
add and gather clocks after counter structure generation for correct Verilog codes
more comments in Counter.scala
add license
add connectResets after add and gather clocks in Counter.scala for correct verilog code of counter wrappers
support reduction operations
merge
Fix asymptotic runtime of createClkDomain
improvements
merge