ARM: remove unnecessary dcache_clean_area

Cortex-A9 has PIPT D-cache which do not require clean the cache
on creating page table.

Original-Change-Id: I42d528be83ea8def96045c7e575c7b3ed95f5980
Reviewed-on: http://git-master/r/40505
Reviewed-by: Heechul Yun <hyun@nvidia.com>
Tested-by: Heechul Yun <hyun@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R214ce4b138abb18e1cfe79465087c39ead248d72

Conflicts:
	arch/arm/include/asm/pgalloc.h
ARM: LPAE: Invalidate the TLB for module addresses during translation fault

During the free_pgtables() call all user and modules/pkmap entries are
removed. If a translation fault for the modules/pkmap area occurs before
we switched away from the current pgd, do_translation_fault() would copy
the init_mm pud into the user pud.

There is a small window between pud_clear() and pmd_free_tlb() in
free_pmd_range() where the pud entry was cleared but the TLB has not
been invalidated yet and the CPU may have cached the original (valid)
pud entry in the TLB. A scenario like below would get stuck in
continuous prefetch abort:

1. Current process exiting. The modules pmd entries not populated
2. exit_mmap() -> ... -> pmd_free_tlb()
3. pud_clear() for the 1GB pud containing user stack and modules (no TLB
   invalidation yet)
4. Interrupt -> module interrupt routine
5. Level 2 (pmd) translation fault occurs when executing the module
   interrupt routine. The CPU previously cached (TLB) the old valid pud
   value for the modules area, so we don't get a level 1 translation
   fault
6. do_translation fault() copies the pud_k into the pud
7. Linux returns to the faulty instruction. Goes back to 5

At point 7, since the CPU still has the old pud value, it goes back to
point 5 and never gets out of this loop. With this patch, the stale pud
TLB entry is invalidated after point 6 and the subsequent prefetch abort
doesn't occur.

Reported-by: Tony Thompson <Anthony.Thompson@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit bb2c1f205618083611d044a461e019c26468a231)

Rebase-Id: R9afbe63e26001dc849f8c55d5f34d6f5e70cfc47
ARM: mm: cache-l2x0: Implement outer_clean_all()

There is already implemented full outer clean routine in
arch/arm/mm/cache-l2x0.c.

Make it possible to use it through outer_cache interface,
like other outer maintenance functions.

bug 983964

Change-Id: I47f1fad536c151c255e6a42d6517114c334ddfef
Reviewed-on: http://git-master/r/116074
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Tested-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Justin Paver <jpaver@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rf769958fea9fd10058a4805eeafe08f5f0e895dd

Conflicts:
	arch/arm/mm/cache-l2x0.c
ARM: dma: Drop GFP_COMP for DMA-IOMMU memory allocations

dma_alloc_coherent wants to split pages after allocation in order to
reduce the memory footprint. This does not work well with GFP_COMP
pages, so drop this flag before allocation.

This patch is ported from arch/avr32
(commit 3611553ef985ef7c5863c8a94641738addd04cff).

Change-Id: I67eb2b15807c36c6a3ade95ee35bf5856d8e0e11
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>

Rebase-Id: Rf13a569ebe836d341cf4d9287ff4b4711dde85cc
ARM: Export LoUIS flush

Export flushing to LoUIS.

Change-Id: If9e3b7119dd4dbe7bdcf6caee5e1632e77b2c288
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/379551
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
ARM: kgdb: ignore breakpoint instructions from user mode

Avoid conflicts with user mode usage of the same instructions, as with
Clang -ftrapv.

Change-Id: I12d1c6d8f94376bfd2503cb0be843d7e478fb6ea
Signed-off-by: Todd Poynor <toddpoynor@google.com>