be: dump prepared graph after intrinsic lowering
tv: set maximum int tarval size to 128bits
amd64: introduce custom mode for xmm registers
amd64: introduce INSN_MODE_128
amd64: spill full 128bit for xmm registers
amd64: support arbitrary entity sizes in MemPerm
amd64: cleanups
amd64: support 128bit xmm consts
amd64: introduce highlevel variants of punpckldq, subpd, haddpd
amd64: allow conversion from/to double vector xmm type
amd64: xmm shuffling trick for ulong -> float conv

I found this neat trick in llvm output, and the existing code was broken
anyway.
amd64: fix missing insn_mode
amd64: change code to get warnings for missing INSN_MODE cases

Also adds a new INSN_MODE_INVALID for 0 to catch uninitialized values.
amd64: fix some wrong modes

Register outputs always need the mode of the register class involved.
ir: Remove redundant and/or wrong comments from ir_init().
ia32: Simplify emit_ia32_IMul().

The noreg is always different to any output register.
ia32: Use arch_get_irn_register() instead of arch_get_irn_register_in() where the operand is already available.
ia32: Move the call to get_ia32_condcode() into determine_final_cc().
ia32: Handle ins_permuted in determine_final_cc().

Some callers did not handle it.
They cannot be permuted (e.g. Jcc).
ia32: Use the generic should-be-same handling for CMovcc.

This avoids the custom emitter, which just duplicated what the generic machinery does.