Revert "msm: mdss: Remove distinction between positive and negative polarities"

This reverts commit db44a1545c3b47fb111685b3a5ec97d93a23df6f.

Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Add SMP parameters into hw capabilites

To handle use cases better, expose smp_mb_cnt and
smp_mb_per_pipe to userspace as part of hardware capability.
Pipes availablity for a use case can be computed taking these
values, based on which, composition decisions can be made.

Change-Id: Ia7cc4db153cdb164a29ae2369d3e991b95aaba65
Signed-off-by: Mayank Chopra <makchopra@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: restrict decimation when layer format is macro-tile

When layer format is macro-tile, decimation cannot be supported. Add the
necessary checks to fail HW configuration for such use-case.

Change-Id: I68adbcdf8014f9ad528e945928f309b221c6dcfd
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: add dynamic clk status check to pipe idle verification

Dynamic clk status of pipe can indicate if that pipe is active or not.
This status in conjunction VBIF halt status of pipe describes the idle
state of the pipe. Add support to parse necessary offsets from DT and
use them to find idle state of the pipe.

Change-Id: I83c6f323d48a85bfc08ff7bcee47f7c3038ea7e1
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: delay freeing buffers for additional vsync

There are cases where if commit happens very close to vsync or in other
uncommon conditions, where MDP will continue fetching from old buffer
address when unmap of the buffer happens. In order to avoid such
scenarios keep a reference of buffers for an additional commit before
unmapping to avoid potential iommu page fault.

Change-Id: Ied61b4851e2d410d71360ad0c119ef21009f91a1
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: ensure pipe is halted before freeing buffers

When pipe is being detached from mixer, there is potential corner case
if underrun occurs at the same time which can cause pipe to flood the
VBIF. On the other hand unmapping a buffer requires VBIF to be idle to
sync TLB, so need to ensure pipe halt is done before freeing the pipe
buffers.

Change-Id: I9686b9d7d17d8dc2a8334157cfa8fa23ba5b47ee
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: prevent dereferencing of user space pointer

We were dereferencing a userspace pointer in kernel.

Change-Id: I128455904cd396690350fc6b784a8844d594539c
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Hold MDP clock Ref count in pan_display path

If handoff fails, the clock ref count becomes 0 and iommu
will get detached. In pan display path, since at that
particular instant iommu gets detached, we use physical
address. After this if iommu is again attached and physical
address is fetched, it can result in continuous IOMMU page
faults. To address this hold MDP clock ref count
in pan display path.

Change-Id: I2370b276acdced2cf22083eb80fcad1b2e454315
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: display: reduce display commit prepare waiting time

Unblock overlay_set, prepare and buffer sync ioctls when
commit thread finishes hardware programming.
Use wait_for_kickoff nstead of pan_idle for these ioctls.

Change-Id: Iefb6cbc390d2130926fdcb93688b4d92bfb26937
Signed-off-by: Ken Zhang <kenz@codeaurora.org>
Signed-off-by: Neti Ravi Kumar <ravineti@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: clock-8974: Allow measurement of clocks in the WCNSS

For debugging reasons, it is required that WLAN drivers
be able to measure clocks in the WCNSS subsystem. It is
assumed that the WCNSS debug mux is already programmed
by the WCNSS firmware.

Change-Id: Ia1bc054f8dd8bd51e62046c9ea71624a22bc890e
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
mdss: display: add mdp core clock to edp control

Since mdss interrupts are generated in mdp core clock domain,
mdp clock need to be enabled along with edp clocks to have edp
interrupt be delivered to edp during edp probe.

Change-Id: Idad19dddfdc2aed9efda15b28b666ac0411dbbda
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: add iommu attach in bus bandwidth control request

Add mdss_iommu_attach in mdss_bus_bandwidth_ctrl to
attach iommu on bus bandwidth enable request.
mdss_iommu_attach/mdss_iommu_dettach can happen in
separate thread, which may lead to a race condition
where attach/detach may happen at same time. Add lock
to properly synchronize the iommu attach/detach to
fix race condition.

Change-Id: I45c8ef1fa1fa1c2da9c6c3702bd007856e469b9d
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Move bus scale table implementation to device-tree

Bus scale table is chip-set dependent where number of paths per
bandwidth use-case can differ chip-set to chip-set. Current
implementation has a static table where it supports only one path per
use-case. Expand MDSS bus scaling implementation to accommodate
chip-sets where more than one path per use-case, i.e. apq8084, is
possible and move table initialization to device-tree so that every
chip-set configures its own table.

Change-Id: Ia6f76654d129fe0ec1a7124aa87b16f96167fe84
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Do not program DSI PLL registers from DSI controller

MDSS DSI driver currently programs certain DSI PLL registers as
part of the DSI PHY off sequence. This is incorrect and could
lead to some unexpected errors such as DSI PLL getting turned off
while the branch clocks are still on. Fix this by removing all
such register programming.

Change-Id: Ie1e88cd18de6b8ef8804f7a2b34b8b8282166c96
CRs-Fixed: 509801
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: add a separate register region for DSI PHY

The DSI PHY register offset from the controller base is
different for different targets. So, add a separate register
region for DSI PHY in the device tree. This register base and
offset will be used to access the DSI PHY registers. Also
change the register offsets which are dependent on the
controller base address.

Change-Id: Ie1d08950f3c8c8801908a1b3cf7db46a44b4e8c3
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: cleanup dsi clock handling

Currently the DSI driver uses a two level reference counting for
the clocks used by the driver so as to ensure that the clocks are
correctly configured for dual-dsi use cases. However, this is not
necessary as the same can be achieved by using a single reference
count. Clean up the code to remove the sub-level ref counts and
add necessary error handling.

Change-Id: I6f1c1bfe83322dc0e1da3d757b6ca88cd629663e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Add support to selectively control bus and link clocks

DSI driver needs two different types of clocks for normal
operation - bus clocks and link clocks. The clock control function
enables/disables both these set of clocks together. However,
under certain circumstances, it is required to control just the
link clocks or the bus clocks. To support this, add separate
ref counts for link and bus clocks and modify the clock control
function to selectively control these clocks.

Change-Id: I25312131fc737b56dc15f4edf5e55a5824dad855
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Turn on DSI link clocks after exiting ULPS

DSI branch clocks should only be enabled after removing the DSI clamps
when exiting the Ultra Low Power State (ULPS). If this is not enforced,
then the RCG for these clocks may not get turned on correctly which
may eventually lead to some display corruption. Fix this by
appropriately modifying ULPS exit sequence.

Change-Id: I5109dd140f8921256f95eb479dd33a73615d489f
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: refactor pipe retrieval and ref count logic

Allow only retrieval of pipes that are on particular framebuffer device
used list. This ensures that pipe is not modified from a different fb
device node and cause potential issues.

Also, modify the ref count logic to use kref and ensure pipe is freed
only while holding mutex in case there could be race condition that
pipe is allocated while being freed.

Change-Id: I626323b5df981a7ed1e03196126cd4376b5ba6a6
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
Signed-off-by: Anusha Koduru <kanusha@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
msm: mdss: Add BTA status check API in DSI controller

Add Bus-Turn-Around (BTA) status check API in DSI
controller to check if it is alive or not. Subscriber
of this API should send relevant notification to user
space for correct action. Update fb driver and cmd
interface to support the BTA failure scenario.

Change-Id: Ic78379b31a48278282182fdba6ba7b2e6f9c26d5
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Dan Trifan <jimsth@gmail.com>