intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
intel: Add MI_LOAD_REGISTER_MEM to intel_decode.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Add DRM_MODE_PAGE_FLIP_ASYNC define

This exposes the kernel API for performing asynchronous flips

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
nouveau: prevent undefined behavior in nouveau_pushbuf_reloc with gcc-4.8

Reported-by: ronald645@gmail.com
Bisected-by (gcc): Andreas Radke <a.radke@arcor.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71116
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
intel/bdw: Add broadwell chipset IDs

v2: Rename s/<SECRET>/IRIS/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
intel/bdw: Handle gen8 bufmgr_init

[bwidawsk: Added Damien's SOB]
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
intel/bdw: Add gen8 to the decode init

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.

Since our aub file dumping's GTT handling is totally fake, we always put
everything in the low 4GB anyway and shouldn't ever need to set
AddressHigh to anything other than 0.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[ben: slight commit message change]
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
intel/bdw: Update MI_BATCH_BUFFER_START for aub dumps

The command now takes a 48bits address and is thus 1 dword longer.

v2 (Ben): commit message: s/byte/dword (Eric)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
intel: Add support for GPU reset status query ioctl

I would have just used the drmIoctl interface directly in Mesa, but the
ioctl needs some data from the drm_intel_context that is not exposed
outside libdrm.

v2: Update based on Mika's kernel work.

v3: Fix compile failures from last-minute typos.  Sigh.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Revert "intel: Add support for GPU reset status query ioctl"

This reverts commit 6335e1d28c422050024bcf4100c4fb3a5bac2afb.

No taxation without representation, in other words no userspace without kernel
stuff being in a stable location, either drm-next but I'll accept drm-intel-next
for intel specific stuff.
radeon: add hawaii chip family

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
radeon: add hawaii pci ids

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
intel: Add support for GPU reset status query ioctl

I would have just used the drmIoctl interface directly in Mesa, but the
ioctl needs some data from the drm_intel_context that is not exposed
outside libdrm.

This ioctl is in the drm-intel-next tree as b635991.

v2: Update based on Mika's kernel work.

v3: Fix compile failures from last-minute typos.  Sigh.

v4: Import the actual changes from the kernel i915_drm.h.  Only comments
on some fields of drm_i915_reset_stats differed.  There are still some
deltas between the kernel i915_drm.h and the one in libdrm, but those
can be resolved in other patches.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
libdrm: bump to 2.4.48
libdrm/mode: Update the encoder and connector defines

Update the defines to match the kernel drm_mode.h

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
intel: Use memset instead of VG_CLEAR

The ioctl expects that certain fields will be zeroed, so we should allow
the helper function to actually work in non-Valgrind builds.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
radeon: fix mipmap level 0 and 1 alignment for SI and CIK

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon: implement 2D tiling for CIK

Bug fixes and simplification by Marek.
We have to use the tile index of 0 for non-MSAA depth-stencil after all.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon: don't overallocate stencil by 4 on SI and CIK

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>