fixed initial state for AF, IX and IY registers
Merge branch 'master' of https://github.com/drhelius/Gearsystem
fixed vdp writing to control register not updating the internal address register
fixed vdp status register returning incorrect data
fixed initial value for vdp register 1
fixed a bug with LDIR, CPIR, INIR, OTIR, LDDR, CPDR, INDR and OTDR not adding cycles correctly
improved vdp timing
Merge branch 'master' into jailbreak