arm64: more SIMD instructions:
ins (vec[], vec[])
mla, mls, mul (vec, vec, vec[])
various more movi/mvni cases
not 16b/8b



git-svn-id: svn://svn.valgrind.org/vex@2883 8f6e269a-dfd6-0310-a8e1-e2731360e62c