Added the DDR3 core and instantiation.

This is a rough implementation. The pinout does not yet match Titan,
the user (internal) interface is tied-off, and DQS and CK0 are
single-ended rather than differential.
Added ddr3_x16 to README
Corrected syntax errors
Updated design to get the DDR3 to route

1) Changed the clock input to the DDR3 core from the sys clock output
of the PCIe core to the oscillator (using the PCIe output clock caused
a routing error)
2) Removed the 1.5V bank voltage setting for the DDR3 pins. This seems
wrong, but changing it resolved the route error.