pico_defconfig: enable ext2/3, exfat (need testers)

Change-Id: Ie8336f76f3b3ce03787233c1022c5b116464eed6
msm: qdsp5: Fix logging adsp messages for 32-bit address

- While enable debugfs for adsp messages to collect
D->A logs, it fails and crashes for camcorder usecase.
- Since in D->A logging, there is 32-bit address
queues for camcorder and print is done using 16-bit
pointer resulting in crash.
- Use 32-bit pointer to access 32-bit address queues
and 16-bit pointer for 16-bit address queues.

CRs-Fixed: 368093
Change-Id: Ia528212699734f1893e77b9be7c7c43e88612492
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
msm: acpuclock-7201: Fix table index for precomputing frequency jump

During acpuclock driver init, we pre compute the next target frequency
row and store its address into up/down indexing array of acpuclock table.
While storing these addresses, we store the data in those array using PLL
number as index of array.

While storing the address, for e.g. if PLL is TCXO it corresponds to array
index -1, then we go ahead and write into location which is beyond the
array address, which is for axi frequency variable; thus it gets corrupted.
Earlier also we had similar corruption of lpj variable, but since we used
to calculate lpj after precomputing so the value was always restored and
this bug was hidden.

To avoid this scenario we can change the enum value for TCXO PLL since
it will not have any impact on driver functionality, however it will
avoid the array index to be equal to -1.

Change-Id: I30a72c55dcce064ed63a9d26ea01a4387280d913
Signed-off-by: Pankaj Kumar <pakuma@codeaurora.org>
msm: acpuclock-7201: Add support for updating lpj in acpuclock

loops_per_jiffy is not updated on SMP systems in cpufreq driver.
So, update the per-CPU loops_per_jiffy value on frequency transition
and also update the other CPUs loops_per_jiffy.

Change-Id: I25db47450e5ac00603c32f928069351ecb827d3e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
msm: acpuclock-7201: Add delay for apps cpu clock switch

While changing the apps cpu clock source, it takes some
time till the clock switch is complete. After clock switch
is complete, then only loops per jiffies must be updated.

Earlier we are updating the loops per jiffies before the
clock switch is complete, which in turn lead to wrong BOGO
MIPS value for that duration for time.

Hence add the delay at appropriate place.

Change-Id: Ide6c7a7dcc5c679b5178420c69691b70ed699a18
Signed-off-by: Pankaj Kumar <pakuma@codeaurora.org>
msm-fb: display: Reducing the display wake up time

100 msec sleep in phy init delays system wake up. Using usleep instead of
msleep to optimize it.

Change-Id: Ibdbb771145210c9462aa68543024be2ae797be4f
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>