board: novena: ddr: Reset FPGA to enable SPD reading

The FPGA is on the same I2C bus as the DDR3 SPD, so when the FPGA is
configured and operational but doesn't configure I2C, then SPD reading
might not work.

As a workaround, reset the FPGA to ensure the lines are free.

Signed-off-by: Sean Cross <xobs@kosagi.com>