mdss: mdp: Add support for partial panel updates

This change programs MDP only for the output resolution (ROI)
set by the client. All staged pipes are cropped to fetch data
only for the resolution programmed.

Change-Id: If06fb36c6ebe167ba369b11a622ab5feaf52172a
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
mdp: mdss: Honor ROI only for interface mixers

When partial update is enabled and we have a valid ROI, crop
source and destination rectangles against ROI only those pipes configured
for interface mixers.

Change-Id: I75111998a43f796f9315b25709e78a568fb1ec0c
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
msm: mdss: Add support to get/set secure flag via an ioctl

Add support to get/set secure flag for WB session through an ioctl.
This is required for WB clients such as AD/WFD, enabling them to modify
or query the secure flag depending on requirements e.g. secure video
playback when using AD.

Change-Id: I852b6f79b31b5ba027d9a5c11561c562023cb99f
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
video: mdss: Fix partial update enable via DT

Change-Id: I3a1eb41769a63a48ff118ccb72583524d0999848

Conflicts:
	drivers/video/msm/mdss/mdss_dsi_panel.c
msm: vidc: Increse OCMEM BW request to enhance performance

There are framedrops observed on high bitrate clips because
OCMEM BW is not sufficient to handle it. Increase OCMEM BW
to avoid framedrops.

Change-Id: I653b416442e56d6e0f0cdfd821c96df4b4f0e1fe
Signed-off-by: Vinay Kalia <vkalia@codeaurora.org>
msm: bam_dmux: tune downlink polling parameters

This change disables the BAM DMUX adaptive timer - this is to address
concerns about drops in TCP throughput for some use cases with the timer
enabled.  It also sets the aggregation to 3ms to save power while not
compromising performance. Power tests show a savings of 3-4% (compared to
having the timer poll the BAM pipe every 1 ms) for LTE (40Mbps downlink and
25Mbps uplink) and HSPA (7Mbps downlink and 384Kbps uplink) with no
degradation in performance.

Change-Id: Ia51eae773723e60d8b051766ad80bfb0a16f5f6d
Signed-off-by: Anurag Singh <anursing@codeaurora.org>
msm: bam_dmux: add loopback support

Bam dmux is currently very difficult to isolate and provide measurements
for common metrics, such as throughput and latency.

Add hooks into bam_dmux to allow for a seperate dynamically
loadable loopback module. This allows bam dmux to be isolated, and to
provide more accurate measurements of the above metrics.

Change-Id: I174d900dea73cca27d32a54a908f43728059be30
Signed-off-by: Brent Hronik <bhronik@codeaurora.org>
msm: bam_dmux: Fix race condition during SSR

BAM DMUX drivers set the global flags to identify the SSR during
SUBSYS_BEFORE_SHUTDOWN notification, but the flags change is not reflected
in some code paths like msm_bam_dmux_write().

Add the SSR flag check and SRCU locking to complete all pending bam dmux
writes before returning the control in SSR call back function for
SUBSYS_BEFORE_SHUTDOWN notification.

CRs-Fixed: 584805
Change-Id: I26647b485977943f272c44f7450ed6c4a4aa62f3
Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
msm: bam_dmux: modify DL low memory algorithm

Bam_dmux maintains a pool of dynamically allocated buffers for the BAM DMA
engine to use as destination memory for Downlink (DL) data.  The allocation
requests for the buffers are done using flags to indicate delays are
tolerable and either the memory or an error should be returned immediately
to bam_dmux as the buffers are normally allocated within various hot paths
inside of the driver.  If a low memory allocation failure is encountered
when attempting to replenish the pool of buffers, bam_dmux will either
attempt the memory allocations later when the next scheduled pool refilling
occurs if there is at least one buffer remaining in the pool, or will
schedule a delayed task to retry the buffer allocation until atleast one
buffer can be put into the pool.

This mechanism of handling low memory situations has two flaws.  First, the
allocation type used by bam_dmux does not trigger the standard low memory
recovery mechanism within the memory management subsystem.  Second, the
peripeheral on the otherside do the DMA engine has a limited hardware based
flow control mechanism that will not release flow control with only one
buffer queued to the DMA engine.

To assist in system recovery, and avoid a data stall, create a cold path
that is tolerant of memory allocation delays and is triggered when the hot
path encounters an allocation failure.

CRs-Fixed: 589665
Change-Id: If72b0eaef285ac6dfd99e97bef1cd7df154e3a48
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
msm: perf: Add L2 support for tracecounters

Add L2 counter output to the tracecounters implementation.
This enables collection of L2 PMU counter values upon context switch.
Set up filtering based on number of L2 counters and number of cores.
Read L2 counter values and display them along with L1 counter values.

Change-Id: I8bbbd251ee52c66505d22ccf037c601013a916f0
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: keep events across hotplug

Keep event list alive across a CPU hotplug so that perf
can resume when the CPU comes back online. Bring a CPU
online when exiting a perf session so it can be cleaned
up properly.

Change-Id: Ie0e4a43f751beb77afdc84e9d52b21780f279d80
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: bring CPU online if needed when disabling irq

When disabling an irq, check that the CPU is online
before trying to run on that CPU. Bring the CPU
online if necessary.

This fixes a problem where a CPU that was not online
when disabling the irq caused the disable and the
free to fail. A subsequent attempt to request the irq
also failed because it had not been freed.

Change-Id: Ib873b5ded83ab843ea4e609f196a31ef0083a213
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Support sw events across hotplug

When CPUs are hotplugged off and on, let the various
sw events continue after the hotplug.

Change-Id: Id1aaf30c459c9cf7c9c38967f9ccad56d4062fd3
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm: perf: initialise krait perf L2 counter enables

Clear the L2 counter enables at initialisation.
They are undefined out of reset.

Change-Id: I957106012625ae09efec47d4f657381963d87a5a
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm: perf: clean up duplicate constraint events

Events with a duplicate constraint are set to state=OFF when detected,
so that their duplicate counts are not read. However, they were not being
cleaned up because the core code only cleaned up ACTIVE events.
This resulted in counters not being freed and eventually running out
of resources.

Clean up the events with state==OFF that were marked that way because of
constraint duplication.
Ensure counts are not updated for OFF events.

Change-Id: If532801c79e6ad6809869eb0a3063774f00c92c3
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Make per-process counters cumulative

In order to get overall value for performance counters, remove reset during
context switches. Add mechanism to calculate deltas for output to the trace
buffer.

Change-Id: I03d894a1b3bd400d8c256c3068f917ed001fbfd9
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: Fix PID for tracepoints

Make previous value of PID a per_cpu variable.
This is required to get the correct value for previous_pid.

Change-Id: I63baf8164ae9226189c745339b122d806901789d
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>
Perf: preserve registers across hotplug

Preserve the registers with userspace bits in them
across hotplug and power collapse. This allows
userspace applications to use the performance counters.

Change-Id: I391563ab770df9aabb5d717b6bc4725750ad0283
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm: perf: fix formatting of trace entry

Remove extraneous comma which breaks processing of
the trace data.

Change-Id: I5fda44cde6a39b16be06c72bc968afc19636b32f
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
msm: perf: Fix cpu id logic in tracectr notifier

The code in tracecounter context switch notifier was using
smp_processor_id() in order to get cpu number. This was resulting
into following dmesg error: "BUG: using smp_processor_id() in
preemptible [00000000] code".
Use thread_info struct to get the cpu #.

Change-Id: Ic7c995d2c2bc25c4389248854dec91fb84ce3128
Signed-off-by: Sheetal Sahasrabudhe <sheetals@codeaurora.org>