AArch32 Support ORN for DIMode

[gcc]
	* config/arm/thumb2.md (*iordi_notdi_di): New pattern.
	(*iordi_notzesidi_di): Likewise.
	(*iordi_notsesidi_di): Likewise.

[gcc/testsuite]
	* gcc.target/arm/iordi_notdi-1.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209613 138bc75d-0d04-0410-961f-82ee72b054a4
Optimise NotDI AND/OR ZeroExtendSI for ARMv7A

[gcc]
	* config/arm/arm.md (*anddi_notdi_zesidi): New pattern.
	* config/arm/thumb2.md (*iordi_notdi_zesidi): New pattern.

[gcc/testsuite]
	* gcc.target/arm/anddi_notdi-1.c: New test.
	* gcc.target/arm/iordi_notdi-1.c: New test case.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209614 138bc75d-0d04-0410-961f-82ee72b054a4
[ARM] Allow any register for DImode values in Thumb2

Ramana commented in the submission email:

    I noticed that for T32 we don't allow any old register for DImode
    values. The restriction of an even register is true only for ARM state
    because the ISA doesn't allow any old register in this place. In a few
    large .i files that I had knocking about, noticed a nice drop in stack
    usage and a generally improved register allocation strategy.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209615 138bc75d-0d04-0410-961f-82ee72b054a4
	PR tree-optimization/60823
	* omp-low.c (ipa_simd_modify_function_body): Go through
	all SSA_NAMEs and for those refering to vector arguments
	which are going to be replaced adjust SSA_NAME_VAR and,
	if it is a default definition, change it into a non-default
	definition assigned at the beginning of function from new_decl.
	(ipa_simd_modify_stmt_ops): Rewritten.
	* tree-dfa.c (set_ssa_default_def): When removing default def,
	check for NULL loc instead of NULL *loc.

	* c-c++-common/gomp/pr60823-1.c: New test.
	* c-c++-common/gomp/pr60823-2.c: New test.
	* c-c++-common/gomp/pr60823-3.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209616 138bc75d-0d04-0410-961f-82ee72b054a4