mtd: nand: omap_gpmc: use macro for register definitions

GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel

Signed-off-by: Pekon Gupta <pekon@ti.com>
mtd: nand: omap: add support for BCH16_ECC - NAND driver updates

This patch add support for BCH16_ECC to omap_gpmc driver.

*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)

Signed-off-by: Pekon Gupta <pekon@ti.com>
am335x: update README for BCH16

updates documentation with explanation on how to select ECC schemes.

Signed-off-by: Pekon Gupta <pekon@ti.com>
am43xx_evm: Add qspiboot target

The ePOS EVM and EVM SK have QSPI as an option to boot.  Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices.  As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.

Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
ti: qspi: populate slave device to set flash quad bit.

The patch populates the slave data which will be used by flash driver to
set the  flash quad enable bit.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
arm:am33xx: Make dram_init call sdram_init() in some contexts

We have two contexts for booting these platforms.  One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads.  The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL.  In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.

In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus).  In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.

Signed-off-by: Tom Rini <trini@ti.com>
arm:am33xx: Rework s_init and add board_early_init_f

With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared.  When SPL booting, this is handled by setting gd
to point to SRAM in s_init.  However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.

Signed-off-by: Tom Rini <trini@ti.com>
keystone: init: enable UART1 to be able use it from kernel

Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.

Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
keystone: k2hk: enable support of nand ecclayout command

Enable support of nand ecclayout command.

Acked-By: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
tam3517: fix NAND detection

commit a0a37183bd7 "ARM: omap: merge GPMC initialization code for
all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND
to be set to access flash. Add CONFIG_NAND for tam3517 derived
boards to prevent the following error: "nand: error: Unable to
find NAND settings in GPMC Configuration - quitting"

cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGS

loadbootenv expects devtype variable to be set. This is missing in
mmcboot command. With this the following error comes:
U-Boot# run mmcboot
mmc0 is current device
SD/MMC found on device 0
** Bad device usb 0 **
** Bad device usb 0 **
Fixing this by setting devtype as mmc.

Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ARM: AM43xx: Fix UART clocks enabling

After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch-am33xx: Add defines for timer0-7

For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.

Also the 'Timer register bits' are expanded.

By the way we add defines for all timers within AM335x SoC.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARD

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/tseries: Add support for using 8-bit on eMMC

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/tseries: only run gpmc_init(...) in NAND-build

if we have no NAND-Chip, we don't need the gpmc-controller and therefore
is no need to init it.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/common: Add CONFIG_CMD_I2C

in almost all cases we need the i2c commands within the u-boot shell.
So we enable them within the common section.

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
board/BuR/tseries: cosmetic changes

Cc: trini@ti.com
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
am43xx: Only read the MPU frequency bits of CTRL_DEV_ATTR

Signed-off-by: Tom Rini <trini@ti.com>
arm:am33xx: Add a scale_vcores() hook

Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher.  Add a similar hook to start with.

Signed-off-by: Tom Rini <trini@ti.com>