OMAP4: ERRATA: ARM: Fix ARM Errata 742230

Errata 742230: This Errata workaround requires bit 4 to be set in the CP15
diagnostic control register. This patch takes care of this errata fix for GP
devices at CPU init time and at the cpu_resume stage.

Change-Id: I5244bec9544fddc9fff33ca2903f5ec19bcc52a7
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: ERRATA: ARM: Fix ARM Errata 751472

Errata 751472: This Errata workaround requires bit 11 to be set in the CP15
diagnostic control register. This patch takes care of this errata fix for GP
devices at CPU init time and at the cpu_resume stage.

Change-Id: I3a8d2b825ac59719233275a77c5fbf5175b35bcb
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: ERRATA: ARM: Fix ARM Errata 743622

Errata 743622: This Errata workaround requires bit 6 to be set in the CP15
diagnostic control register. This patch takes care of this errata fix for GP
devices at CPU init time and at the cpu_resume stage.

Change-Id: I6b9cf510ca631f74da4ce2f31c1190a2216aa5bb
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: Update ARM errata options.

WARNING: NOT FOR OMAP4430!

OMAP4460 apparently uses PL310 r3p1-50rel0, which according to the existing config docs and this link don't effect it: http://www.spinics.net/lists/arm-kernel/msg343612.html

The newly added ones do effect it.

Signed-off-by: Dan Trifan <jimsth@gmail.com>
defconfig: errata changes

Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4+: Add ability to store reboot reason

Bootloaders need to know when their platforms do a reboot.
The only memory that is retained is SAR ram accross reboots,
provide ability to store the reboot reason in a standard location
in the SAR memory (using the last 0xf bytes in SAR BANK1 ram).

This is now populated with the string "normal" if the reboot
is due to ordinary reboot commands, if the reboot reason is
for other reasons, such as bootloader or recovery as is the
case with Android systems, this stores the same.

NOTE: bootloader should be updated accordingly.

Change-Id: I32d05ef023682a1530b34315dac90fd97bed3265
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP4: HSOTG: Improved HSOTG USB EYE diagram

1. Added the ability to improve HSOTG USB EYE diagram.

 solution #1: (all 44XX CPUs family)
   Improvement of 2-3% in EYE diagram opening by playing slightly on USB
   driver output impedance.

 solution #2: (4430 CPUs)
   Improvement of up to 8% in EYE diagram opening has been accomplished by
   decreasing the internal termination impedance by increasing the SWCAP
   trim code in USBPHY_USB2PHYCM_TRIM register to 0x24.

2. Added menuconfig option for this feature:
   'System Type'--->'OMAP 44XX HSOTG Eye diagram correction'

Change-Id: Ifd0450e8eeea57e6f68d1e166fe878a39ce52f71
Signed-off-by: Volodymyr Riazantsev <x0153367@ti.com>
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
OMAP: Support for Android RAM console

Android's RAMCONSOLE framework is handy framework which allows
saving the kernel printk messages to a buffer in RAM, so that
after a kernel panic they can be viewed in the next kernel
invocation, by accessing /proc/last_kmsg.

This obviously needs DDR to be in selfrefresh mode. Board files
which have relevant support need to enable CONFIG_OMAP_RAM_CONSOLE
and call omap_ram_console_init with relevant parameters for this
to function.

Change-Id: I2dd5ad55a0a3af5a5dcb9a9b8a797e1371af39bc
Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com>
Signed-off-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
init: debug: bye bye

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
writeback: Fix occasional slow sync(1)

In case when system contains no dirty pages, wakeup_flusher_threads()
will submit WB_SYNC_NONE writeback for 0 pages so wb_writeback() exits
immediately without doing anything. Thus sync(1) will write all the
dirty inodes from a WB_SYNC_ALL writeback pass which is slow.

Fix the problem by using get_nr_dirty_pages() in
wakeup_flusher_threads() instead of calculating number of dirty pages
manually. That function also takes number of dirty inodes into account.

CC: stable@vger.kernel.org
Reported-by: Paul Taysom <taysom@chromium.org>
Signed-off-by: Jan Kara <jack@suse.cz>
Signed-off-by: Cristoforo Cataldo <cristoforo.cataldo@gmail.com>
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
i think this needs applied as well

Signed-off-by: Dan Trifan <jimsth@gmail.com>
mm/ksm: engage deferred timer by default

Signed-off-by: Paul Reioux <reioux@gmail.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: 6995/2: mm: remove unnecessary cache flush on v6 copypage

Originally introduced to maintain coherency between icache and dcache
in v6 nonaliasing mode. This is now handled by __sync_icache_dcache since
c0177800, therefore unnecessary in this function.

Signed-off-by: Heechul Yun <heechul@illinois.edu>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: mm: Add v7_flush_dcache_by_level() API.

On ARMv7 based SOC with an integrated L2 cache, there is a need
to have a flush API to operate on each cache level. In few low power
modes, L2 cache is retained where as L1 is lost. The current
v7_flush_dcache_all(), flushes all the levels and
it would be quite expensive.

So introduce v7_flush_dcache_by_level() API which takes a
parameter (cache level), and flush only on that level.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: mm: Optimise the v7 Dcache flush all routine.

The current algorithm flushes using the SET and WAY, where it iterates over
a given SET in all the WAYS and to the next SET. Change this so that every
successive flush address will go to in to the alternate EMIF(1/2), there by
utilising the full bandwidth. Also iterating all the SETS of a given WAY,
and then switching to the next way can reduce the possibility of frequent
change in the row bits during successive transactions of the DDR memory.
This will help in reducing the ROW open/close time.

Signed-off-by: Marquette Anderson <m-anderson13@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: mm: Avoid the use of r8 register in cache flush all/level apis.

Currently cache_flush_by_level API is called from __v7_setup.
At this point, r8 contains the initial TTBR1 base address.
But r8 is not saved/restored in the API, resulting in corrupting
it. So when the corrupted r8 is used further during the
boot sequence, causes weird issues.

The issue becomes evident when the ARM workaround to use
"TTBR1 instead of reserved ASID during the context switch"
is applied.

Fixing this by optimising the code to avoid using r8.

Also there was a issue with optimise patch corrupting r3.
This has no functional impact, but resulted in unnessecary
cmp instructions.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Dan Trifan <jimsth@gmail.com>
mm: memcg: only evict file pages when we have plenty

Commit e9868505987a ("mm, vmscan: only evict file pages when we have
plenty") makes a point of not going for anonymous memory while there is
still enough inactive cache around.

The check was added only for global reclaim, but it is just as useful to
reduce swapping in memory cgroup reclaim:

    200M-memcg-defconfig-j2

                                     vanilla                   patched
    Real time              454.06 (  +0.00%)         453.71 (  -0.08%)
    User time              668.57 (  +0.00%)         668.73 (  +0.02%)
    System time            128.92 (  +0.00%)         129.53 (  +0.46%)
    Swap in               1246.80 (  +0.00%)         814.40 ( -34.65%)
    Swap out              1198.90 (  +0.00%)         827.00 ( -30.99%)
    Pages allocated   16431288.10 (  +0.00%)    16434035.30 (  +0.02%)
    Major faults           681.50 (  +0.00%)         593.70 ( -12.86%)
    THP faults             237.20 (  +0.00%)         242.40 (  +2.18%)
    THP collapse           241.20 (  +0.00%)         248.50 (  +3.01%)
    THP splits             157.30 (  +0.00%)         161.40 (  +2.59%)

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Acked-by: Michal Hocko <mhocko@suse.cz>
Acked-by: Rik van Riel <riel@redhat.com>
Acked-by: Mel Gorman <mgorman@suse.de>
Cc: Hugh Dickins <hughd@google.com>
Cc: Satoru Moriya <satoru.moriya@hds.com>
Cc: Simon Jeons <simon.jeons@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Backport to 3.0: Boy Petersen <boypetersen@gmail.com>

Signed-off-by: Dan Trifan <jimsth@gmail.com>
mm,vmscan: only evict file pages when we have plenty

If we have more inactive file pages than active file pages, we skip
scanning the active file pages altogether, with the idea that we do not
want to evict the working set when there is plenty of streaming IO in the
cache.

However, the code forgot to also skip scanning anonymous pages in that
situation.  That leads to the curious situation of keeping the active file
pages protected from being paged out when there are lots of inactive file
pages, while still scanning and evicting anonymous pages.

This patch fixes that situation, by only evicting file pages when we have
plenty of them and most are inactive.

[akpm@linux-foundation.org: adjust comment layout]
Signed-off-by: Rik van Riel <riel@redhat.com>
Cc: Mel Gorman <mel@csn.ul.ie>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: Dan Trifan <jimsth@gmail.com>
video: omap2: displays: disable Content Adaptive Brightness by default
to workaround known reboot at screen-off issue on first boot Lockscreen
when disabled by tweaking apps

Signed-off-by: Dan Trifan <jimsth@gmail.com>
ARM: mm: Flush only CPU local cache instead of all cache levels.

The ARMv7 processor setup functions clean and invalidates the
cpu cache before enabling MMU. The intention here is to start
with clean CPU local cache.

But on architectures like Cortex-[A15/A8], this code will end
up flushing the L2 cache as well which undesirable and incorrect.
The setup functions are used in CPU hotplug scenario's too and
hence flushing all cache levels should be avoided.

Fix this code by restricting the cache flush to local cpu
cache or L1.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Dan Trifan <jimsth@gmail.com>