ARM: dts: imx6qdl-sabrelite: Add HDMI

Adds hdmi with DDC on i2c2.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: dts: imx6qdl-sabrelite: Add parallel display

Add parallel display RS800480T-7X0GP-A on DI0.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: dts: imx6qdl-sabreauto: Add parallel display

Add parallel display RS800480T-7X0GP-A on DI0. Disabled by
default due to a pin conflict with AUDMUX.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Enable/disable DI clock in crtc fb enable/disable

Commit 45dfde0a4e60165bc48c72031c08f14551469fa0 split out DI clock
enable/disable from DI module enable/disable, so we need to explicitly
call ipu_di_{enable|disable}_clock() during crtc fb enable/disable.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: dts: imx6qdl: Create imx-drm crtc nodes

Create imx-drm crtc device nodes. Each crtc node requires the following
parameters:

- parent ipu phandle.
- di number.
- port endpoints.

Optionally the node can specify a "dual-plane" boolean parameter
to configure the crtc device with a foreground plane. If not given,
the crtc will have only a single plane.

The crtc port lists the endpoints to the remote encoder endpoints.
These endpoints were moved out of the ipu nodes, since they more
logically now belong to the crtc nodes.

As a result, the display-subsystem node should enumerate its crtcs
instead of the former ipu ports.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Remove IPU client registration

The IPU client devices have been moved to the device tree, so
remove platform registration of those devices. As a result,
platform data (struct ipu_client_platformdata) is no longer
needed, the client data is retrieved from the device nodes.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: Crtcs moved to device tree

The crtcs are now nodes in the device tree, and the encoder endpoints
fall under the crtc port.

ipu_client_platformdata is no longer needed and is gone. The crtc
retrieves the following required parameters from its node:

- ipu phandle.
- di number.
- the port endpoints.

Optionally, "dual-plane" can be specified to configure the crtc device
with a foreground plane. If not given, the crtc will have only a
single plane.

The DC and IDMAC channels can be inferred from the dual-plane parameter.
In table form, the channel usage is:

                 Background Plane   Foreground Plane     Single Plane
                 ----------------   ----------------     ------------
    Flow Type    IDMAC   DC   DP     IDMAC   DP           IDMAC   DC
    ---------    -----  ---  ---     -----  ---           -----  ---
    Sync          23     5    0       27     1             28     1
    Async         24     6    2       29     3             41     2

Async flows are included in the above table but async displays are
not yet supported by the crtc and plane drivers.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di

AS pll5_video_div has already been used as clock root for ldb_di,
so use pll2_pfd0_352m as clock root of ipu_di for HDMI.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>

Cherry-picked from d18ac68c937552f67baaa500d7d56e79f408ccf4.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: hdmi: optimize i2c write wait

It seems wait around 50 ~ 100 micro seconds is enough to allow
I2C Master PHY done, so instead of wait 1000 usec at each time
of register check, wait 100 usec is more appropriate.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>

Ported from cdb4cfc65dfcdf46894dac609141a01cd831bd79.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-di: Set rate of DI pre clock

This patch sets the rate of the DI pre clock to support a much wider
range of pixel clock frequencies.

It does this by calculating two values for the pre-clk rate: a
rate that is a whole integer multiple of the pixel clock, and a rate
that is a half-integer multiple. It then programs whichever rate
comes closest to generating the desired pixel clock, and uses the
corresponding integer or half-integer divider.

The reason only whole or half integer DI dividers are used is because
of a chip bug in the fractional part of DI Base Sync Clock Gen 0 register
(see discussion in FSL community site at
https://community.freescale.com/thread/308577).

Quoting from that thread:

"Pixel IPU clock for Display has high jitter and does not have 50% duty cycle.
This is expected behavior, when the clock divider is set to a value that is not
an integer. When the divider is set to a non-integer value, the average
frequency of the clock will be correct, but the clock will jitter."

According to our experimentation, only 0x8 for the fractional part seems
to generate clock waveforms that are tolerated by most displays (this
hasn't been proved officially).

Based loosely on 794a1916f9fb0ce7cfc80d981f43ab9f09dd69c5.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
gpu: ipu-v3: Add RGB666 interface pixel map

Adds RGB666 to the pre-loaded interface pixel maps.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: parallel-display: Support RGB666 pixel fmt

Add a clause to imx-pd driver to use 18-bit output if driver is told so.

Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>

Ported from 23bddaa0530458c4f76c881c189f266bb0f4b073.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
ARM: i.MX6: select pll3_usb_otg for ldb_di

Select pll3_usb_otg for ldb_di clock for rev 1.0 chips.

Based on 2d34ce03cbbbf15213825f51e232fd6d4dd5cee4.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: imx-ldb: Add debug to connector/encoder entry points

Add some debug macros for the important encoder and connector
callbacks.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: imx-ldb: Implement imx_ldb_encoder_dpms()

Implement imx_ldb_encoder_dpms(). Two new functions are created
to share poweroff and poweron code. imx_ldb_poweroff() is called
by encoder dpms, prepare, and disable. imx_ldb_poweron() is called
by encoder dpms and commit.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: parallel-display: Fix typo when setting mode type

Comma expression is used to set mode type
"mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,"
which is a typo, replace it with ";".

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>

Ported from 1e8af135d09cc478b83ccb6280dbc34f6d585317.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*

Pass a drm pixel format fourcc to ipu_cpmem_set_yuv_interleaved(),
ipu_cpmem_set_yuv_planar_full(), and ipu_cpmem_set_yuv_planar(),
instead of a v4l2 pixel format. The remaining cpmem API that still
accepts a v4l2 format is now only ipu_cpmem_set_image(), since this
function is called by v4l2 drivers.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()

Adds ipu_drm_fourcc_is_planar(), which is equivalent to
ipu_pixelformat_is_planar() but accepts a drm fourcc format.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: ipuv3-plane: Fix planar formats

During a mode set the U/V plane strides and buffer offsets
for planar pixel formats were not being configured in cpmem.
Fix by calling ipu_cpmem_set_yuv_planar() for planar formats.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
imx-drm: ipuv3-plane: Allow YUV space for background plane

A background plane was assuming the framebuffer pixel format was
RGB by passing IPUV3_COLORSPACE_RGB to ipu_dp_setup_channel(). Fix
by passing the actual colorspace of the framebuffer's pixel format.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>