clk-composite: init best_rate and use abs()
prevent compiler warnings about clk being uninitialized

It doesn't happen with my gcc-4.7 but there were reports about it
fix softrst issues found by Jack
pinctrl: rockchip: generalize bank-quirks

Upcoming Rockchip SoCs have additional quirks to handle. Currently they would
be handled by giving the bank a special compatible property. But the nature
of the new quirks would require a lot of them. Also as we want to move to the
separate dw_gpio driver in the future, these bank-definitions should be
extended at all.

Describing the bank quirks this way also enables us to deprecate the special
bank compatible string for bank0 on rk3188 and simplify the handling code.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: precalculate iomux offsets

An upcoming SoC introduces an interesting quirk to iomux handling making the
calculation of the iomux register-offset harder. To keep the complexity down
when getting/setting the mux, precalculate the actual register offset at
probe-time.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: add support for 4bit wide iomux settings

In the upcoming rk3288 SoC some iomux settings are 4bit wide instead of
the regular 2bit. Therefore add a flag to mark iomuxes as such and adapt
the mux-access as well as the offset calculation accordingly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: enable iomuxes from pmu space

The upcoming rk3288 moves some iomux settings to the pmu register space.
Therefore add a flag for this and adapt the mux functions accordingly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: support unrouted iomuxes per bank

On the upcoming RK3288 SoC contain some unrouted pins in their banks. So while
for example pin8 of bank5 stays pin8 with all its settings (register offset etc),
pins 0 to 7 are not routed outside the SoC at all.
Therefore add a flag to mark these unrouted iomuxes to prevent people from using
them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
pinctrl: rockchip: add support for rk3288 pin-controller

The pin-controller of the new RK3288 contains all the quirks just added in
the previous patches.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
documentation: add rockchip spi documentation

Signed-off-by: addy ke <addy.ke@rock-chips.com>
spi: add driver for Rockchip RK3xxx SoCs integrated SPI

In order to facilitate understanding, rockchip SPI controller IP design
looks similar in its registers to designware. But IC implementation
is different from designware, So we need a dedicated driver for Rockchip
RK3XXX SoCs integrated SPI. The main differences:

- dma request line: rockchip SPI controller have two DMA request line
  for tx and rx.

- Register offset:
                  RK3288        dw
  SPI_CTRLR0      0x0000        0x0000
  SPI_CTRLR1      0x0004        0x0004
  SPI_SSIENR      0x0008        0x0008
  SPI_MWCR        NONE          0x000c
  SPI_SER         0x000c        0x0010
  SPI_BAUDR       0x0010        0x0014
  SPI_TXFTLR      0x0014        0x0018
  SPI_RXFTLR      0x0018        0x001c
  SPI_TXFLR       0x001c        0x0020
  SPI_RXFLR       0x0020        0x0024
  SPI_SR          0x0024        0x0028
  SPI_IPR         0x0028        NONE
  SPI_IMR         0x002c        0x002c
  SPI_ISR         0x0030        0x0030
  SPI_RISR        0x0034        0x0034
  SPI_TXOICR      NONE          0x0038
  SPI_RXOICR      NONE          0x003c
  SPI_RXUICR      NONE          0x0040
  SPI_MSTICR      NONE          0x0044
  SPI_ICR         0x0038        0x0048
  SPI_DMACR       0x003c        0x004c
  SPI_DMATDLR     0x0040        0x0050
  SPI_DMARDLR     0x0044        0x0054
  SPI_TXDR        0x0400        NONE
  SPI_RXDR        0x0800        NONE
  SPI_IDR         NONE          0x0058
  SPI_VERSION     NONE          0x005c
  SPI_DR          NONE          0x0060

- register configuration:
  such as SPI_CTRLRO in rockchip SPI controller:
    cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
        | (CR0_SSD_ONE << CR0_SSD_OFFSET);
    cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
    cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
    cr0 |= (rs->tmode << CR0_XFM_OFFSET);
    cr0 |= (rs->type << CR0_FRF_OFFSET);
  For more information, see RK3288 chip manual.

- Wait for idle: Must ensure that the FIFO data has been sent out
  before the next transfer.

Signed-off-by: addy ke <addy.ke@rock-chips.com>
Merge commit 'refs/top-bases/topgit/devel' into topgit/devel