issue #5: Update required verilator version
On Mavericks, if the value passed to __builtin_clz/ctz is zero, it returns a random result.

Fixed simluator to properly return 32 in these cases, as expected by this architecture.
Tweak behavior of atomic memory transactions

load_sync should always acquire the cache line in the exclusive state
store_sync cannot generate a cache miss.  If the line has been evicted, it should fail.
Rename read->load in some places to be more consistent
Rename variables to be clearer
Merge branch 'master' into v2-write-through

Conflicts:
	rtl/v2/core/dcache_data_stage.v
	rtl/v2/core/instruction_pipeline.v
	rtl/v2/core/writeback_stage.v