mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes

chip->ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)

Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this.
This patch
(1) removes omap_hwecc_init() and omap_hwecc_init_bch()
as chip->ecc.hwctl will re-initializeGPMC before every read/write call.
omap_hwecc_init_bch() -> omap_enable_ecc_bch()

(2) merges the GPMC configuration code for all ECC schemes into
single omap_enable_hwecc(), thus adding scalability for future ECC schemes.
omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc()

Signed-off-by: Pekon Gupta <pekon@ti.com>
mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes

chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.

All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndrome from GPMC controller.

This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way:
- merges multiple chip->calculate API for different ECC schemes
  omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw()
				==> omap_calculate_ecc()
- removes omap_ecc_disable() and instead uses it as inline.

Signed-off-by: Pekon Gupta <pekon@ti.com>
mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes

chip->ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
	for ECC_BCH8 scheme using GPMC and software lib/bch.c
(c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
	for ECC_BCH8 scheme using GPMC and ELM

This patch updates (c)
- checks for calc_ecc[]==0x00 so that error_correction is not required for
  known good pages.
- adds scalability for other ECC_BCHx scheme by merging following
  omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch()
- fixing logic for bit-flip correction based on error_loc[count]

Signed-off-by: Pekon Gupta <pekon@ti.com>
board/ti/am335x/README: update for NAND boot

NAND boot mode on AM335x EVM has been verified, and steps
to use it has been documented and update in this README

Signed-off-by: Pekon Gupta <pekon@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Acked-by: Tom Rini <trini@ti.com>
drivers: net: cpsw: add support to have phy address from cpsw platform data

Some platforms like AM437x have different EVMs with different phy addresses,
so this patch adds support for passing phy address via cpsw plaform data.
Also renamed phy_id to phy_addr so better understanding of the code.

Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335
pengwyn boards]
Signed-off-by: Tom Rini <trini@ti.com>
ARM: AM43xx: clocks: Enable CPGMAC clock control

Enable CPGMAC clock control for AM43xx to use ethernet in U-Boot

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
ARM: AM43xx: Add CPSW support to AM43xx EPOS and GP EVM

Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected
to RMII and RGMII phy respectively and enable cpsw in config.

Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
ARM: AM335x: add support for reading cpsw 2nd mac address from efuse

Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also adding mii command support to am335x common config.

Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
ARM: DRA7xx: add support for reading cpsw 2nd mac from efuse

Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also correct the bit masking of mac id read from the efuse.

Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
ARM: AM4372: Update EMIF registers for DDR3

Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like
400MHz the read latency expected will be CL+3 as per tests from HW
folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team
to come back for better explanation).

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ARM: AM43xx: Add Ethernet boot support to SPL

Add Ethernet Boot support to SPL

Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
ARM: AM43xx: EMIF: configure self-refresh entry delay

Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl
and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the
desired delay in cycles that the EMIF waits without an access to enter
self-refresh, in this case 8192 cycles. With this, code desiring to
enter self refresh only has to toggle one bit to enable it.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: AM43xx: Write sdram_config to secure_emif_sdram_config

The register secure_emif_sdram_config in control module is copied to
the EMIF sdram_config register when it is coming out of DeepSleep0 in
order to ensure that the EMIF comes up for the correct type of DDR.
Without this, resume can hang from within the kernel.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
ARM: AM43xx: Change DDR3 Reset Value

The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value
of the ddr reset value for DDR3 before the EMIF takes over. We must have
this bit set high so that on exit from DeepSleep0 within the kernel the
reset line has the proper value.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup

Since the switch may be re-configured for VLAN usage in Linux (or any
other OS), lets reset the switch to its default register values upon
power-up. Otherwise network might not be available in U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Lukas Stockmann <lukas.stockmann@siemens.com>
Cc: Tom Rini <trini@ti.com>
MIPS: fix types u64 and __u64 to unsigned long long

Linux MIPS uses asm-generic/int-ll64.h in asm/types.h.
Thus u64 and __u64 are defined as unsigned long long. Port this
over to U-Boot.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
malta: correct tcl script path in README.malta

README.malta referred to board/malta, but malta has now been moved
within board/imgtec/, so correct the path.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Merge branch 'master' of git://git.denx.de/u-boot-mips
mtd: nand: omap: remove redundant platform specific header: arch-xx/omap_gpmc.h

Currently there are two sets of omap_gpmc.h header files
(a) arch/arm/include/asm/omap_gpmc.h
 common header file for all platforms, containing defines and declarations used
 by GPMC NAND driver.

(b) arch/arm/include/asm/arch-xx/omap_gpmc.h
 SoC platform specific header file containing defines like ECC layout.

This patch removes platform specific arch-xx/omap_gpmc.c because:
 - GPMC hardware engine is common for all SoC platforms hence only (a) is enough
 - ECC layout is now defined in omap_nand.c driver itself based on ecc-scheme
   selected. Hence all ECC layout declarations in (b) are redundant.

Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>
mtd: nand: omap: remove unused #defines from common omap_gpmc.h

OMAP NAND driver can detect Page-size and OOB-size of NAND device from ONFI
params or nand_id[] table. And based on that it defines ECC layout.
This patch
1) removes following board configs used for defining NAND ECC layout
	- GPMC_NAND_ECC_LP_x16_LAYOUT (for large page x16 NAND)
	- GPMC_NAND_ECC_LP_x8_LAYOUT  (for large page x8 NAND)
	- GPMC_NAND_ECC_SP_x16_LAYOUT (for small page x16 NAND)
	- GPMC_NAND_ECC_SP_x8_LAYOUT  (for small page x8 NAND)

2) removes unused #defines in common omap_gpmc.h depending on above configs

Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5

Signed-off-by: Pekon Gupta <pekon@ti.com>