Name of exit function in exit.c

Change the name of the exit function to _exit as suggested in clib
documenation for all gcc_arm toolchains (GCC_ARM and CoIDE)
[NUCLEOs] Improvement of gpio_irq hal

Now it is possible to have multiple interrupt pins on EXTI vectors.
Example:
EXTI0 -> PA_0 or PB_0 or PC_0, ... only 1 pin
EXTI5_9 -> PA_5 and PA_6 and PB_7 and PC_8 and PC_9: up to 5 pins
EXTI10_15: PA_10 and PB_11 and PB_12, ... : up to 6 pins
Modified Terminal setting for New GR-PEACH.

Modified Terminal setting of Ethernet and LED PIN for New GR-PEACH.
Tools: Export for nrf51dk and dongle to GCC ARM and uvision
Added IAR Export RTOS CORTEX M3
[NUCLEO_F030R8] exporter for gcc and coide
[NUCLEO_F072RB] exporter for gcc and coide
[NUCLEO_F0xx] build_travis and build_release

Add NUCLEO_F030 and NUCLEO_F072 to build_travis. Extend toolchainlist of
both targets in build_release.
Merge pull request #734 from 0xc0170/dev_nrf51_xx_exporters

Tools: Export for nrf51dk and dongle to GCC ARM and uvision
Merge pull request #737 from ohagendorf/NUCLEO_F030R8_F072RB_export_gcc_coide

Tools: NUCLEO_F030R8, NUCLEO_F072RB - export to gcc_arm and coide
Merge pull request #720 from bcostm/master

Targets: NUCLEOs - Improvement of gpio_irq hal
Added IAR Export RTOS CORTEX M3
IAR exporter Rtos clean
[NUCLEO_F0] Add PeripheralPins files
[NUCLEO_F103RB] Add PeripheralPins files
[NUCLEO_F3] Add PeripheralPins files
[NUCLEO_F4] Add note on optional pins
[NUCLEO_L0/L1] Add PeripheralPins files
Fixed LPC1768 NVIC placement space in RAM
removed comments and fixed USB_RAM section