Add a simple skeleton for streaming_processor

Also define register_address_t
Add streaming_processor to .xise
Wire up reg_dir in streaming_processor
Merge master into streaming_processor
[SP] Add ALU and predicate logic
pc testbench
Add and wire ALU. Wire SP in processor
Merge branch 'master' into streaming_processor
Implement and wire a block of SPs
Merge pull request
Add generation of id adders in streaming block
Merge branch 'master' into id_adders

Conflicts:
	vhdl.xise
Merge pull request #5 from dmpro2014/id_adders

Id adders
Merge in master