[adc5g] Changes to reset logic.

The MMCM is now reset using dcm_reset instead of ctrl_reset, this signal is driven high
by the OPB pcore right after reset.

The FIFO is reset when the MMCM is not yet locked or when ctrl_reset is driven high by
the OPB pcore. This is controllable via software.
[adc5g] Expanded the o0_allowed values to include 1.0 for the MMCM.

This was previously set to 2:128 but 1 is actually an allowable value.
Also simplified xps_adc5g.m by using the ismember function instead of
checking if MMCM parameters are within the top/bottom of allowable
values.
Update "defaults" of files modified in 25a5046

Commit 25a5046 added reg_retiming=on to some Delay blocks that are setup by
some mask init scripts.  Unfortunately, reg_retiming is not a parameter of the
blocks in question, so their mask initialization scripts will not redraw
existing blocks because same_state() will return true for these blocks.

To ensure that blocks drawn prior to adding "reg_retiming=on" will be redrawn
even if no other parameters have changed, "reg_retiming=on" is being added to
these blocks' "defaults" cell arrays even though "reg_retiming" is not a
parameter of these blocks.  This iwll ensure that same_state will return false
for these blocks until they are redrawn with reg_retiming=on and the new
defaults array goes into the calculation of their saved state.
Update "defaults" of files modified in eb0a525

Commit eb0a525 added reg_retiming=on to some Delay blocks that are setup by
some mask init scripts.  Unfortunately, reg_retiming is not a parameter of the
blocks in question, so their mask initialization scripts will not redraw
existing blocks because same_state() will return true for these blocks.

To ensure that blocks drawn prior to adding "reg_retiming=on" will be redrawn
even if no other parameters have changed, "reg_retiming=on" is being added to
these blocks' "defaults" cell arrays even though "reg_retiming" is not a
parameter of these blocks.  This iwll ensure that same_state will return false
for these blocks until they are redrawn with reg_retiming=on and the new
defaults array goes into the calculation of their saved state.
Make feedback_osc delays use behavioral HDL

This (theoretically) makes the delays more amendable to register retiming.
Also added reg_retiming=on to the "defaults" array of this block to ensure
that existing instances of this block will redrawn.
Add reg_retiming=on to more Delay blocks

Add reg_retiming=on to Delay blocks in the barrel_switcher, cmult,
complex_conj, and fft_direct blocks.  Also added reg_retiming=on to the
"defaults" arrays of these blocks to ensure that existing instances of these
blocks will redrawn.
Make fft_stage_n_init warning more informative

The warning displayed when overriding delays_bram=on (due to delay being
shorter than bram_latency) now includes the stage at which this warning was
issues as well as an indication of what bram_latency and the delay values are.
Make addrees counter in delay_bram use HDL

The address counter in delay_bram now has "use behavioral HDL" checked.

A "block_version" field was added to the "defaults" array.  This is used to
force existing blocks to be redrawn even though the block's interface (i.e.
mask init function) has not changed.
[gen_xps_mod_ucf] Added ability to add user-specified constraints to system.ucf

This can be accomplished by setting the USER_UCF_PATH environment variable to a
directory containing files with the .ucf extension. Each of these files is then
appended to the end of system.ucf.
Force delay_brams=off if delay <= bram_latency

In fft_stage_n_init, the delays were forced to be in slices (i.e. NOT BRAMs) if
the delay length was less than the BRAM latency.  In fact, the delays should
(and now are) forced to be in slices if the delay length is less than OR EQUAL
TO to BRAM latency.  The newly added "or equal to" part is needed because using
BRAM delays requires that the delay be greater than BRAM latency.
Fix biplex_core's determination of delay type

The biplex_core now determiens whether to use BRAMs or slices for the delays by
checking the delay length against the threshold length.  Previously it had
included the input bit width into the calculation, but this led to using more
BRAMs than desired.

Also added a check to ensure that BRAMs are not used if the delay length is not
greater than the BRAM latency.  This will prevent warnings from
fft_stage_n_init iabout overriding the use of BRAMs.
Add qdr2 and qdr3 options to qdr_transpose mask

FWIW, this change was done via a text editor so it might actually be mergeable.
Merge branch 'ddr3_devel'
Merge branch 'davidm'
Robustified the effects of setting IDCTRL_100.

Now when this variable is set the tools will instantiate *TWO*
IDELAYCTRLs, one with a hacked 100 MHz reference clock and the
other with normal 200 MHz reference clock. The 100 MHz IDELAYCTRL
is then grouped with the IODELAYs of the QDR's while the other
should by default be used for any other IODELAYs.

This should in theory not break any existing designs if the
IDCTRL_100 environment variable is not set but if it is set the
QDR calibration may succeed at certain fabrics clock rates without
breaking calibration of any other core (for example, the DDR3 core).