[AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212677 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Resurrect LowerSDIV24

Use ComputeNumSignBits instead of checking for i8 / i16.

If an integer is known to fit in 24-bits, we can
do division faster with float ops.
R600: Add FMA instruction
R600: Match rcp node
XXX - fsub fmul mad pattern