tools: test also LVDS input on pexarria5
monster: remove configurable PLL skew

The problem with using the PLL phase shifter to compensate skew between
the LVDS-PLL and transceiver clock inputs is that you cannot shift the
LVDS serdes clock. Thus you need to put the settings directly into the
PLL's megawizard. Fortunately, it seems that LVDS compensation mode
happens to have the correct phase offsets by default for our board!
syn: refresh project files with hdlmake
Merge branch 'asterisk' into proposed_master