target-mips: ll generates AdEL for unaligned addr

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
softmmu: Add size argument to do_unaligned_access()

Pass data size arguement to do_unaligned_access().
It is unable to find if an access spans two pages without data size
in the call back function.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
target-mips: Misaligned Memory Accesses for R6

Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However, misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).

MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS64
Architecture, Appendix B Misaligned Memory Accesses.
Available at http://www.imgtec.com/mips/architectures/mips64.asp

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
target-mips: Misaligned Memory Accesses for MSA

MIPS SIMD Architecture vector loads and stores require misalignment support.
MSA Memory access should work as an atomic operation. Therefore, it has to
check validity of all the addresses for the operation.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
target-mips: fix to clear msacsr

fexdo, fexupl and fexupr missed to clear msacsr

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Merge pull request #20 from yongbok/i6400-mips64r6-PRIP4

Misaligned Memory Accesses for R6 and MSA
Fix to clear MSACSR for fexdo, fexupl and fexupr

Updates for #17 

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>