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2014-08-26  Jan-Benedict Glaw  <jbglaw@lug-owl.de>

	* config/tc-moxie.h (md_convert_frag): Silence warning.
Fix a typo in the selection pattern for the or1knd cpu.

	* config.bfd: Fix typo in or1knd selection.
MIPS/gas/testsuite: Remove ECOFF offset alternatives

This complements commit 16e5e222b6eae6f110ea72bf627585c095a453a8,
removing offset values embedded in dump patterns that served ECOFF
binaries.

	* gas/mips/l_d.d: Remove ECOFF offset alternatives.
	* gas/mips/mips1@l_d.d: Likewise.
	* gas/mips/ld.d: Likewise.
	* gas/mips/mips1@ld.d: Likewise.
	* gas/mips/mips1@ld-forward.d: Likewise.
	* gas/mips/s_d.d: Likewise.
	* gas/mips/mips1@s_d.d: Likewise.
	* gas/mips/sd.d: Likewise.
MIPS/gas: SAA/SAAD macro clean-ups

This change removes code duplication for the SAA macro in line with other
such macros and also adds a !microMIPS internal consistency guard as
there's no microMIPS encoding of the underlying SAA/SAAD instructions.

	* config/tc-mips.c (macro) <M_SAA_AB>: Remove duplicate code and
	jump to...
	<M_SAAD_AB>: ... here.  Assert that !microMIPS.
MIPS: Make the CODE10 operand code consistent between ISAs

This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
	"sdbbp", "syscall" and "wait".

	include/opcode/
	* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
	over to `+J'.
Fix linker testsuite failures for Aarch64.
Resolves PR 17312

	* ld-aarch64/eh-frame-foo.s: Use 8-byte offset for X30.
	* ld-aarch64/eh-frame-bar.s: Likewise.
	* ld-aarch64/eh-frame.d: Updated to match current readelf output.
	* ld-elf/eh5.d: Allow any register names.
[AArch64] Improve copy relocation support on four absolute relocation types

2014-08-26  Jiong Wang  <jiong.wang@arm.com>

  bfd/
	* elfnn-aarch64.c (elfNN_aarch64_check_relocs): Initialize non_got_ref
	properly for MOVW_G0/1/2_NC and MOVW_G3.  Reject them when linking
	shared library.
	(elfNN_aarch64_gc_sweep_hook): Add check on these relocs.

  ld/testsuite/
	* ld-aarch64/copy-relocs-so.s: New test file.
	* ld-aarch64/copy-relocs-exe.s: Likewise.
	* ld-aarch64/copy-relocs.d: New expectation file.
	* ld-aarch64/emit-relocs-264-bad.d: New test file.
	* ld-aarch64/emit-relocs-266-bad.d: Likewise.
	* ld-aarch64/emit-relocs-268-bad.d: Likewise.
	* ld-aarch64/emit-relocs-269-bad.d: Likewise.
	* ld-aarch64/aarch64-elf.exp: Run new added test.
[ARM] Update selected_cpu based on info got during parsing

  gas/
    * config/tc-arm.c (aeabi_set_public_attributes): Update intended_arch based
    on the info we got during parsing.
    (arm_handle_align): Make sure the p2align expanding logic under thumb
    unchanged.

  gas/testsuite/
    * gas/arm/blx-bl-convert.d: New testcase.
    * gas/arm/blx-bl-convert.l: Warning expectation.
    * gas/arm/blx-bl-convert.s: Source file.
Disambiguate test for relaxation type.

* elf32-rl78.c (rl78_elf_relax_section): Disambiguate test for
relaxation type.
rl78.h (RL78_RELAXA_MASK): New.  Relax types are enums, not bits
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