Added Some Sequential Circuits

__1. Rewrote `SR` and `D` - Uses Gate Level design__

SR and D will now use Connector class for its input and output and more importantly __use clock as one input__. All flip flops have been implemented as Negative Edge triggered. Edge is found by storing a one bit clock history.

__2. Created `JK` and `T` - Uses Behavioural Model__

__3. Created a new file [ `counters.py` ]__

__4. Added `Counters` Class as base for all counters.__

Counters are triggered by Negative edge triggered clock pulses

__5. Using `Counters` Class, created two counters `BinaryCounter` and `NBitRippleCounter` [can have N bits - N is the variable that will be passed as a parameter]__

__6. Created tests for all the FlipFlops and Counters.__

__7. Created Examples for all the FlipFlops and Counters.__