msm: cpr: Enable CPR support for 8625

CPR (Core Power Reduction) helps save CPU power by
reducing the chip voltage whenever possible

Change-Id: Ifa32967046b4bb7f5b4f756feb9cefabe8f5bea4
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/devices-msm7x27a.c
msm: platsmp-8625: Add support for Quad Core 8625Q

Add 8625Q specific code to support quad-core environment.

Change-Id: I6517c1699539cfa9cc8845b87d44ef91322e4115
Signed-off-by: tirupathireddy <tirupath@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/platsmp-8625.c
msm: Kconfig: Add support for MSM_FIQ for 8625

On 8x25 modem is the master processor and in case apps
is holding lock with irqs disabled then sending an SMSM reset
interrupt does not help and the state of Apps is not known
at all.Hence we are enabling a FIQ which will save the cpu context
of the apps and help debugging before going into SMSM reset.
In the current patch we are adding support for enabling the fiq
and defining the fiq offset number.

Change-Id: Ie97f808e610724328c638a9580f3de535e3e9a28
Signed-off-by: Taniya Das <tdas@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/Kconfig
Perf: 8625 L1CC PMU support

Add perfevents support for the 8625 L1CC PMU.

Change-Id: I254c5278c25fa337cdcbe2ee157569ec123eb247
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: Perf: Add 9625 L1 PMU support

Enable the L1 cache controller performance monitoring
unit on the 9625, so that its counters can be controlled
via the perfevents framework.

Change-Id: I4f7f305a4fb119223494bd0c306e834742904286
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/include/mach/irqs-9625.h
ARM: cache_l2x0: Set outer_cache resume

Set the outer_cache.resume function during l2x0_init and declare a static
inline void version to allow compilation when OUTER_CACHE is not defined.
The outer_cache functions are used for L2 cache management in chips that
have an external cache controller. The outer_cache.resume re-enables the
L2 cache controller and is called when exiting power collapse.
This change is needed to allow drivers to call outer_cache API's instead
of directly using the APIs defined in cache-l2x0.c and thus avoid having
to use #ifdef macros in the code.

Change-Id: Ifc7d25f905e3248f864c9eaf019436968e77b8a2
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>

Conflicts:
	arch/arm/mm/cache-l2x0.c
ARM: perf: add L2x0 PMU driver

This patch adds initial support for the PMU featured in the L2x0
series of Level 2 Cache Controllers, supporting L220 & PL310.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Change-Id: I04d54f5b2586264ac3325a0ed19c452d25f8fd4c
[ashwinc@codeaurora.org: Remove unused functions for passing compilation.]
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Conflicts:
	arch/arm/include/asm/hardware/cache-l2x0.h
msm: Perf: Add 9625 L2 PMU support

Enable the L2 cache controller performance monitoring
unit on the 9625, so that its counters can be controlled via the
perfevents framework.

Change-Id: I22f6b1fd1e3e8c57cbbd419d724ec7b81f910b0a
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/Kconfig
msm: Perf: Add PL310 support for the 8625 and 7627A

Enable perf events support for the PL310 L2CC. Include
single kernel image support for both targets.

Change-Id: Iaad714b538782638a6a299e11dbb1d989b38a563
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/Kconfig
	arch/arm/mach-msm/devices-msm7x27a.c
	arch/arm/mach-msm/include/mach/irqs-7xxx.h
	arch/arm/mach-msm/mpm-8625.c
perf: Add L2 cache PMU counters support for 8625q

Added L2 cache PMU counters support for 8625q devices.

Change-Id: I78d436b89b7d38f9188f5e6cdba83b130b47e97f
Signed-off-by: Gautam Akiwate <gakiwate@codeaurora.org>
msm: perf: Add PL310 perf support for 9615

Include the perfevents driver for the PL310 L2CC
on the 9615.

Change-Id: I0d5df49bdeff5804488245921e73a05c589d2a47
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: perf: add debug patch logging framework

Provide a mechanism to track which msm perf patches
are present in a kernel. Some kernel branches do
not include all patches which causes problems trying
to debug perf issues. This framework provides a way
to keep track of which patches have been included
in a build.

Change-Id: Ib8ef311454564c4609d94decd93e039c80104275
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Restore counter after powercollapse for generic ARM PMU's

The MSM SoC's which have ARM's CPU's can power collapse. Ensure
the CPU side PMU's correctly restore the counters after coming
out of power collapse.

Change-Id: I544a1dd8ced26f726ba115d14867d9e34c2a7944
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Toggle PMU IRQ when CPU's are hotplugged

When a CPU is hotplugged out while a perf session
is active, disarm the IRQ when the CPU is preparing
to die. This ensures that perf doesn't lock up when
it tries to free the irq of a hotplugged CPU.
Similarly, when a CPU comes online during a perf session
enable the IRQ so that perf doesn't try to disable
an unarmed IRQ when it finishes.

Change-Id: Ic4e412e5f1effae0db34a3e4b5e7e5c65faed2a0
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
arm: Remove no-longer-required RCU_NONIDLE wrapper

Commit 21111be8 "ARM: Fix negative idle stats for offline cpu" moved call
to cpu_die() to occur outside of rcu_idle_enter()/rcu_idle_exit() section.
As a result, the RCU_NONIDLE() wrapper to complete() call in
arch/arm/kernel/process.c:cpu_die() is no longer required (and is
technically incorrect to have). Removing RCU_NONIDLE() wrapper also removes
this warning seen during CPU offline:

[Note: Below message has been edited to fit 75-char per line limit.
Insignificant portions of warning message has been removed in each line.]

------------[ cut here ]------------
WARNING: at kernel/rcutree.c:456 rcu_idle_exit_common+0x4c/0xe0()
Modules linked in:
(unwind_backtrace+0x0/0x120) from (warn_slowpath_common+0x4c/0x64)
(warn_slowpath_common+0x4c/0x64) from (warn_slowpath_null+0x18/0x1c)
(warn_slowpath_null+0x18/0x1c) from (rcu_idle_exit_common+0x4c/0xe0)
(rcu_idle_exit_common+0x4c/0xe0) from (rcu_idle_exit+0xa8/0xc0)
(rcu_idle_exit+0xa8/0xc0) from (cpu_die+0x24/0x5c)
(cpu_die+0x24/0x5c) from (cpu_idle+0xdc/0xf0)
(cpu_idle+0xdc/0xf0) from (0x8160)
---[ end trace 61bf21937a496a37 ]---

Signed-off-by: Srivatsa Vaddagiri <vatsa@codeaurora.org>
Change-Id: I721e6b20651674e6f6f584cf8d814af00b688c91
Perf: Correct irq for CPU hotplug detection

The platform data was requesting the wrong number,
it should request the first perf irq item.

Change-Id: I4a25b4704ed9e76172c6b0d4ca4b28a3286ab2ad
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Check perf activity on correct CPU

The CPU hotplug notifier is not always preempt safe.
So relying on smp_processor_id() is not correct.

Use the cpu id from the notifier as the target
CPU to check for perf activity before hotplug or power
collapse.

CRs-Fixed: 454688
Change-Id: I1a96b236904a2c8ae2f82bbceab4ca8a195395d1
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Revert "ARM: allow the kernel text section to be made read-only"

This reverts commit e5e483d13369ab62d95f1738edce3cd64c7ca2ff.

This change breaks LPAE support. Other patches provide the same
functionality so just revert the patch.

Change-Id: Iea1e88064a1618ca1fc9d717ee5a4ffe77681745
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
ARM: mm: Remove SW emulation for ARM domain manager

8x50 is no longer supported in the msm-3.4 kernel, so remove this
feature.

Change-Id: I2156ef22cca82d3cce6a7d39e366b93cab32f811
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Conflicts:
	arch/arm/include/asm/domain.h
	arch/arm/mm/fault.c