hdl/modules/fmc_adc_common/*: add option to use an external referece clock

Add option to use an external supplied clock (usually from
another PLL or global clock buffer inside the FPGA) to clock
the data to downstream FPGA logic. This implies the ASYNC FIFO
after the first ADC acquisition and the synchronization betweem
multiple ADC channels.

This is useful when instantiating more than one ADC module, as
we don't need two reference clocks and more than one reference
would only make things harder.
hdl/modules/dbe_wishbone/*: update FMC ADC modules

As the previous commit changed the interface of the
ADC module, we update them here
hdl/top/ml_605/*: update FMC ADC instantiaton in top files

The interface for the FMC ADC module have changed, so we
update them here in the top files
hdl/*/*_adc_common/fmc_adc_pkg.vhd: add ref clk function

As the ref_clk equal to "c_num_adc_channels" means
"external reference clock" we use a function to generate
the correct reference clock in all cases
hdl/modules/dbe_wishbone/*: use ref clk function

Replace direct usage of ref_clk generic by the
f_adc_ref_clk () function, which correctly selects the
adc ref clk in all cases, even when using an external
reference
hdl/*/*_adc_common/fmc_adc_iface.vhd: use ref clk function internally

The g_ref_clk is out of bounds when using external clock
reference. So, we must use the f_adc_ref_clk () function
hdl/ip_cores/dsp-cores: update submodule reference
hdl/modules/*/wb_ethmac_adapter/*: update to new etherbone core

The xwb_ethmac_adapter component uses compoenents from
the Etherbone core. As its naming has changed a while ago,
we need to update the components interfaces here
hdl/modules/fmc_adc_common/*: fix 7SERIES idelay primitives

For 7SERIES FPGAs, the iodelay primitive has beed updated to
idelaye2. So, we add a differente generate for these FPGAs
hdl/modules/*: add g_delay_type on FMC ADC modules

Exposed the idelay type desired to user. This brings flexibility
on selecting the different delay types for different FPGA devices
hdl/*/*/fmc_adc_buf.vhd: fix wrong IOSTANDARD

For single-ended inputs, it is necessary to use
A single-ended standard, obviously
hdl/modules/fmc_adc_common/*: add option to disable bufmr

On 7-SERIES FPGAs, we need to explicitily instantiate a
BUFMR primitive in order to use a MRCC pin as a drive to
a Multi-Region BUFR or BUFIO. Now, we can select which ones
of used clocks are LOCed to MRCC pins and which ones
are not.
hdl/top/afc_v1: add new top files for the AFCv1 board

Warning: MAP and PAR can take a long time due to
poor placement of the GTP tranceiver for the PCIe
core
hdl/syn/afc_v1: add new syn file for the AFCv1 board
hdl/top/top/afc_v1/*: add divclk generic to PLL

This allow us to select a broader range of frequencies,
in order to generate a 100 MHz clock from a 125 MHz clock
source, for instance
hdl/top/afc_v1/*: fix wrong timing constraint in UCF file

This constraint was causing conflicts with the other
ones and a wrong PLL PERIOD contraint was taken into
account
hdl/top/afc_v1/*: change MMCM_ADV to PLLE2_ADV primitive

In the 7-SERIES families, the PLL and MMCM are two separate
primitives, very similar to each other. In other to reduce
the number of MMCM usage, we changed it to PLL here
hdl/modules/*/wb_fmc130m_4ch.vhd: comment out unused signals

Thse were causing lgic contention with some specific Xilinx
XST options, particularly KEEP_HIERARCHY = SOFT, to keep
the hierarchy so we could properly apply some AREA constraints.
The tool would GND these NETS anyway.
hdl/modules/*/fmc_adc_buf.vhd: change LVDS to LVCMOS

For single-ended pins, we can't use LVDS standard,
so we default to LVCMOS25. If the standard is actually
different from this, we could still override it in the UCF
file
hdl/modules/*/fmc_adc_data.vhd: add attributes to keep pipeline

If we let the synthesis tool in its defauts attributes, the
pipeline gets removed and moved into a SRL primitive, causing
PCBs having ADC FMC data lines routed to oppositte FPGA I/O
banks to not meet timing. With these attributes we intruct
XST and MAP to keep the pipeline and not suck them into an
SRL, which would hurt the ability by MAP and PAR to move
the pipeline registers around to meet timing.