FPGA: Use inverted output of DCM instead of adding inverter on clock line
FPGA: Don't use ODDR2 for glitchly clock outpu
FPGA: Updates to clock glitch generation
FPGA: Update UCF for CW-Lite
Merge branch 'master' of git.assembla.com:chipwhisperer
Merge branch 'master' of git.assembla.com:chipwhisperer